Clock Dropout Protection Circuit for Continuous Sync Output
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock synchronization systems in electrical charging systems face challenges in maintaining a continuous clock signal when the external clock signal is invalid, leading to potential stalling or damage in power converters and other circuitry.
Innovation Solution
A dropout protection circuit that includes a synchronization control circuit, an internal clock generator, and an output circuit, which determines the validity of the external clock signal and seamlessly switches between the external and internal clock signals to ensure continuous clock availability, using a bandpass filter and validity logic to assess clock signal quality and a multiplexer to select the appropriate clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phase-locked loop-based systems are used for clock synchronization, then clock signal continuity can be maintained, but system complexity and power consumption increase
Solution Approach 1:
The patent extracts only the essential functionality needed for clock dropout protection - a simple validity detection mechanism that switches between external and internal clock sources - without implementing a full phase-locked loop system. This selective extraction maintains clock continuity while eliminating unnecessary complexity and power consumption associated with complete PLL implementations.
Solution Approach 2:
The patent employs a simpler, less expensive clock validation and switching mechanism instead of costly phase-locked loop circuits. The solution uses basic signal detection and multiplexing components that are cheaper and consume less power while achieving the same reliability goal of maintaining continuous clock operation.
2Reliability
If phase-locked loop-based systems are used for clock synchronization, then clock signal continuity can be maintained, but power consumption increases
Solution Approach 1:
The patent replaces power-hungry phase-locked loop circuits with a simpler clock validation and switching mechanism that consumes significantly less power. The solution uses minimal active components for signal detection and multiplexing, achieving clock continuity without the high power consumption inherent in PLL-based systems.
Solution Approach 2:
The patent extracts only the power-critical functionality of clock continuity maintenance while removing the power-intensive phase-locked loop mechanisms. This selective approach keeps essential clock synchronization protection while eliminating the power consumption burden of complete PLL implementations.
3Productivity
If external clock signal is not validated, then system operation can proceed, but stalling or damage may occur in power converters
Solution Approach 1:
The patent implements preliminary validation of the external clock signal before the system proceeds with operation. The validation logic checks clock signal integrity in advance, and the multiplexer is pre-configured to switch to the internal clock source if validation fails, preventing stalling or damage before they can occur.
Solution Approach 2:
The patent applies preliminary anti-action by detecting invalid clock signals in advance and preemptively switching to the internal clock source. This preventive measure counteracts potential harm to power converters by ensuring a valid clock signal is always present before critical operations commence.
Data Source
AI summary
In a described example, a circuit includes a synchronization control circuit having a sync input and a sync control output, in which the sync input is coupled to a sync terminal configured to receive an external clock signal. An internal clock generator circuit has a control input and an output. The control input is coupled to the sync control output. An output circuit has first and second signal inputs, a mode control input and a clock output. The first signal input is coupled to the sync input, and the second signal input of the output circuit is coupled to the output of the internal clock generator circuit. The mode control input is coupled to the sync control output, and the clock output adapted to be coupled to a controller.