Clock Duty Cycle Correction with Dual-Edge Phase Alignment
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Solution Overview
Problem
Conventional duty cycle correction systems, such as delay lock loops, face challenges in achieving fast and accurate control over the duty cycle of clock signals, particularly in high-speed data transfers, due to limitations in phase detection frequency and alignment of rising and falling edges.
Innovation Solution
A duty cycle correction system that includes a duty cycle adjustor and phase detectors to align transitions of clock signals, allowing for precise adjustment of the duty cycle by delaying either the rising or falling edge of the input clock signal, ensuring a 50% duty cycle through a process involving inverters and variable delay lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional delay lock loop is used to generate clock signals for latching data on both rising and falling edges, then data latching capability is improved, but duty cycle control accuracy deteriorates due to phase detection limitations
Solution Approach 1:
The phase detection function is segmented into two separate phase detectors: one dedicated to detecting rising edges and another for falling edges. This segmentation allows each detector to operate independently and optimally, resolving the contradiction by enabling precise duty cycle control through separate detection of each edge type rather than using a single phase detector that compromises accuracy.
2Device complexity
If phase detection is performed once per clock period in a conventional DLL, then device complexity is reduced, but control speed deteriorates
Solution Approach 1:
The useful action of phase detection is made continuous by having two phase detectors operating simultaneously on different edges of the same clock signal. While a conventional DLL performs phase detection once per period, this invention continuously monitors both rising and falling edges, doubling the effective detection frequency and control speed without significantly increasing overall system complexity.
3Device complexity
If rising and falling edges are not properly aligned in a conventional DLL, then device complexity is minimized, but manufacturing precision deteriorates
Solution Approach 1:
The invention implements feedback control by using the output of both phase detectors to generate control signals that are fed back to the delay lines. The first phase detector's output controls the first delay line to align rising edges, while the second phase detector's output controls the second delay line to align falling edges. This dual feedback mechanism ensures precise edge alignment without requiring overly complex control logic.
Data Source
AI summary
Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the duty cycle adjustor. First and second phase detectors have first inputs coupled to the duty cycle adjustor through an inverter and second inputs coupled to the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.