Clock Duty Cycle Calibration Circuit for PLL Reference Stability
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Solution Overview
Problem
The stability of the clock duty cycle in reference clock signals is inadequate, leading to inaccuracies in clock duty cycle calibration circuits, which affects the quality of communication signals in wireless communication systems.
Innovation Solution
A clock duty cycle calibration circuit comprising a duty cycle calibration cell, delay matching cell, signal frequency multiplier cell, phase-locked loop cell, and calibration control cell, which work together to align and adjust the duty cycle of the calibration clock signal to a target value, enhancing accuracy by compensating for duty cycle offsets due to temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If clock multiplier technology is used to increase the frequency of the phase-locked loop reference clock signal, then the phase noise performance of the phase-locked loop is improved, but the stability of the clock duty cycle of the reference clock signal deteriorates
Solution Approach 1:
The patent implements a duty cycle calibration circuit that uses feedback mechanisms to continuously monitor and adjust the duty cycle of the reference clock signal. The calibration control cell samples the calibration clock signal and generates calibration control signals based on the sampled results, forming a closed-loop feedback system that maintains duty cycle stability even when frequency is increased through clock multiplication.
Solution Approach 2:
The patent changes the duty cycle parameter of the reference clock signal through calibrated adjustment. The duty cycle calibration cell modifies the duty cycle parameter in response to calibration control signals, enabling the system to maintain optimal duty cycle values despite frequency changes introduced by clock multiplier technology.
2Measurement precision
If the duty cycle of the reference clock signal is calibrated, then the accuracy of the calibration clock signal is improved, but the complexity of the circuit increases
Solution Approach 1:
The patent divides the duty cycle calibration function into separate modular cells: a duty cycle calibration cell, a delay matching cell, a frequency multiplier cell, and a calibration control cell. Each cell performs a specific function, making the overall calibration system more manageable and maintainable while achieving high accuracy through coordinated operation of these segmented components.
3Measurement precision
If delay matching processing is performed on the calibration clock signal, then the alignment accuracy with the reference clock signal is improved, but the time required for calibration increases
Solution Approach 1:
The patent performs delay matching processing as a preliminary step before frequency multiplication and phase-locked processing. The delay matching cell pre-aligns the calibration clock signal with the reference clock signal by adjusting delay parameters, ensuring that subsequent calibration operations start with properly synchronized inputs, which reduces overall calibration time while maintaining high alignment accuracy.
Data Source
AI summary
A clock duty cycle calibration circuit, method, and clock multiplier circuit, wherein the clock duty cycle calibration circuit uses the calibration control cell to perform a first sampling process on the delay-matched clock signal using the first feedback clock signal when the phase-locked loop cell is in the first locked state, can acquire a first sampled signal that used to instruct the relationship between the actual duty cycle of the calibration clock signal and the target duty cycle, then the calibration control cell generates the first calibration control signal according to the first sampled signal, thereby enable the duty cycle calibration cell to maintain the duty cycle of the calibration control signal at the target duty cycle according to the first calibration control signal, that can overcome duty cycle offset caused by operating temperature, which helps improve the accuracy of the generated calibration clock signal.