Clock Duty Cycle Measurement Using Delta-Sigma Feedback

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Solution Overview

Problem

Operating duty cycles of digital circuits can drift over time, leading to deviations from the desired 50% duty cycle due to component interactions and changes in operating conditions such as voltage and temperature.

Innovation Solution

A duty cycle measurement (DCM) device utilizing a first-order delta-sigma analog-to-digital converter to measure the duty cycle of a clock signal with high accuracy, featuring a clock select circuit, a charge pump circuit, and a clocked comparator circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a clock signal is used to sequence digital circuit operations, then the circuit can perform sequential operations, but the duty cycle may drift over time due to component interactions and operating conditions

Engineering Contradiction:
Improveduty cycle stabilityVSAvoidduty cycle consistency
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent implements a feedback mechanism by measuring the actual duty cycle of the clock signal and comparing it to the desired 50% duty cycle. Based on this comparison, the system adjusts the clock signal generation to correct duty cycle deviations, thereby maintaining reliable operation despite component variations and environmental changes.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system dynamically changes the clock signal parameters by adjusting the duty cycle based on measured values. The duty cycle measurement device monitors the clock signal characteristics and the system responds by modifying the clock signal generation parameters to maintain the desired 50% duty cycle, compensating for drift caused by operating conditions.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If the duty cycle of a clock signal is required to be precisely maintained at 50%, then the circuit operation accuracy is improved, but measurement and adjustment mechanisms increase device complexity

Engineering Contradiction:
Improveduty cycle measurement accuracyVSAvoidmeasurement device structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces a duty cycle measurement device as an intermediary component that specifically measures the duty cycle of the clock signal. This dedicated measurement mechanism provides accurate duty cycle information without significantly complicating the overall system, as it focuses on a single measurement function rather than comprehensive signal analysis.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs self-measurement and self-adjustment of the duty cycle. The duty cycle measurement device monitors the clock signal generated by the system itself, and the system uses this measurement information to automatically adjust its own operation, eliminating the need for external measurement equipment and reducing overall device complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250180644A1Device and Method for Measuring a Duty Cycle of a Clock Signal
Publication Date: 2025.06.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250180644A1 patent drawing
  • US20250180644A1 patent drawing
  • US20250180644A1 patent drawing

AI summary

A duty cycle measurement (DCM) device includes a charge pump circuit and a clocked comparator circuit. The charge pump circuit is configured to receive a clock signal that has an unknown duty cycle and to generate a capacitor voltage based on the duty cycle of the clock signal. The clocked comparator circuit is configured to receive the capacitor voltage and a reference voltage and to generate a digital output code based on the capacitor voltage and the reference voltage. The digital output code is indicative of the duty cycle of the clock signal. The charge pump circuit is further configured to receive the digital output code. A method of determining a duty cycle of a clock signal is also disclosed.