Clock Duty Correction Circuit for Offset-Calibrated Memory Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed semiconductor memory devices face reliability issues due to errors in measuring and correcting the duty ratio of clock signals, which are exacerbated by variations in environment parameters such as process, voltage, and temperature, leading to potential malfunctions and decreased operation margins.
Innovation Solution
A semiconductor memory device with a duty correction circuit that includes a clock edge detector, a duty detector, and a code counter, which performs an initial measurement operation to remove offsets and accurately measure and correct the duty ratio of the clock signal by generating detection pulses and comparison signals, and using a code counter to control the duty detector and adjust the clock signal phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the critical dimension is scaled down to increase integration, then device functionality is improved, but measurement error increases
Solution Approach 1:
The patent applies preliminary action by performing an initial measurement operation before the actual duty ratio measurement. This initial measurement captures offset values that are then subtracted from subsequent measurements, thereby eliminating systematic errors that would otherwise increase with scaled-down dimensions. The offset calibration is performed in advance to prepare the measurement system for accurate operation at smaller critical dimensions.
Solution Approach 2:
The patent implements feedback by using the initial measurement results to correct subsequent duty ratio measurements. The offset values obtained from initial measurement are fed back into the measurement process to compensate for systematic errors, creating a closed-loop correction mechanism that maintains measurement precision even as device dimensions are scaled down.
2Speed
If the clock signal period is decreased to increase operating speed, then data processing speed is improved, but error ratio increases
Solution Approach 1:
The patent performs preliminary offset measurement and storage before high-speed operation begins. This preliminary action establishes a reference baseline that remains valid even when the clock period is reduced, allowing accurate duty ratio measurement to be maintained at higher operating speeds without proportionally increasing error.
Solution Approach 2:
The measurement system uses feedback by continuously comparing subsequent duty ratio measurements against the offset value established during initial measurement. This feedback mechanism compensates for the increased error ratio that would otherwise result from reduced clock periods, maintaining measurement accuracy despite higher operating speeds.
3Device complexity
If duty ratio measurement is performed without initial offset removal, then device complexity is reduced, but operation reliability decreases
Solution Approach 1:
The patent incorporates preliminary offset measurement as a one-time initialization step that occurs before normal operation. This preliminary action removes systematic offsets from the measurement system, thereby improving reliability without requiring continuous complex correction mechanisms during operation. The offset calibration is performed once and then used for all subsequent measurements.
Solution Approach 2:
The system uses feedback by applying the offset correction value obtained from initial measurement to all subsequent duty ratio measurements. This feedback approach maintains high operation reliability by compensating for systematic errors while avoiding the need for continuously complex measurement circuits, as the correction is applied based on pre-established offset data.
Data Source
AI summary
Semiconductor memory device with duty correction circuit includes a clock edge detector configured to generate first and second detection pulses in response to a transition timing of a common clock signal in an initial measurement operation; a duty detector configured to compare the first and second detection pulses to output comparison result signals; and a code counter configured to control the duty detector based on the comparison signals outputted from the duty detector in the initial measurement operation.