Clock Duty-Cycle Power Throttling for ML ASIC Power Surges
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Solution Overview
Problem
Current methods fail to accurately monitor and throttle power consumption in hardware-based machine learning (ML) systems like ASICs, leading to inaccurate power management and unintended consequences due to sudden power surges, which can exceed system capabilities.
Innovation Solution
A hardware-based programmable architecture that directly measures power consumption and adjusts it to fit a desired power profile by modifying the clock signal's duty cycle without changing the frequency, using a power measurement engine, power throttling signal generator, and power throttling engine to initiate and control power throttling based on defined limits and thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If power consumption is monitored by inferring from chip activity metrics, then power management can be implemented, but the power measurement is inaccurate
Solution Approach 1:
The patent introduces a current sensor as an intermediary device that directly measures current drawn by the chip, converting the abstract power monitoring problem into a concrete electrical measurement. This intermediary component provides accurate power data without requiring complex inference algorithms from multiple chip activity metrics.
2Use of energy by moving object
If clock frequency is changed to throttle power consumption, then power consumption is reduced, but unintended consequences occur in other parts of the chip
Solution Approach 1:
The patent applies local quality by selectively applying power throttling only to specific processing tiles or functional units that are exceeding power limits, rather than globally reducing clock frequency across the entire chip. This localized approach reduces power consumption in problematic areas while maintaining normal operation in other parts of the chip.
3Speed
If sudden power surges are allowed to meet high performance requirements, then processing speed is improved, but thermal generation exceeds system support
Solution Approach 1:
The patent implements a feedback mechanism where thermal sensors continuously monitor temperature in different regions of the chip. When thermal thresholds are approached, the system automatically triggers power throttling in affected regions, creating a closed-loop control system that balances performance and thermal management in real-time.
4Use of energy by moving object
If power throttling is applied to reduce power consumption, then power consumption is reduced, but processing performance decreases
Solution Approach 1:
The patent employs dynamic power management where the degree of power throttling is continuously adjusted based on real-time power consumption measurements and thermal conditions. The system can dynamically scale power delivery to match actual workload requirements, maintaining high performance when needed while reducing power consumption during lower-demand periods.
Data Source
AI summary
A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.