Clock Edge Monitoring Circuit for Narrow Glitch Detection
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Solution Overview
Problem
Conventional EMFI sensors for detecting clock glitches are large, technology-dependent, power-hungry, and require trimming, failing to efficiently protect devices from narrow glitches that can cause misbehavior.
Innovation Solution
A compact clock signal monitoring unit using four flip flops and a delay element, optimized for both clock edges, with a fixed delay adapted to expected frequency and PVT conditions, providing robust glitch detection without trimming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional EMFI sensors are used to detect clock glitches, then clock glitch detection capability is provided, but the device area increases, power consumption increases, and trimming is required
Solution Approach 1:
The monitoring function is divided into multiple flip-flops (first, second, third, fourth) that are cross-coupled and distributed across different clock phases. Each flip-flop handles a specific portion of the clock cycle monitoring, allowing parallel detection without requiring a single large sensor block.
Solution Approach 2:
The same flip-flop structure and delay element are reused multiple times in the circuit to achieve both rising edge and falling edge glitch detection. The cross-coupled flip-flops serve dual purposes of state storage and glitch detection, eliminating the need for separate dedicated sensor circuits.
2Reliability
If conventional EMFI sensors are used to detect clock glitches, then clock glitch detection capability is provided, but power consumption increases
Solution Approach 1:
The monitoring is performed periodically synchronized with the clock signal edges. Flip-flops are clocked only on specific edges (rising or falling), and the delay element is activated only when needed to detect potential glitches, rather than continuously operating at full power.
Solution Approach 2:
The cross-coupled flip-flop structure automatically detects glitches through its inherent feedback mechanism. When a glitch occurs, the state changes in one flip-flop trigger a corresponding change in the other, generating a detectable output without requiring additional active monitoring circuits.
3Reliability
If conventional EMFI sensors are used to detect clock glitches, then detection function is provided, but trimming is required for correct operation
Solution Approach 1:
The delay element is designed with a fixed delay value that is predetermined to be appropriate for the expected clock frequency range. This fixed parameter approach eliminates the need for post-fabrication trimming, as the delay is inherently suited for the application without requiring adjustment.
Solution Approach 2:
The circuit uses standard, off-the-shelf flip-flop components and a simple delay element that can be implemented with basic logic gates. These are replaced or reset if needed, rather than requiring complex trimmed components, simplifying the manufacturing process.
4Ease of manufacture
If a delay element with fixed delay is used adapted to expected frequency, then trimming is eliminated and area is reduced, but adaptation to frequency variations is limited
Solution Approach 1:
The delay element is designed with a delay value that covers the expected operating range with some margin. Rather than attempting to perfectly adapt to all possible frequency variations, the delay is set to provide sufficient detection capability for the primary operating conditions, accepting limited performance at extreme frequencies.
Data Source
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AI summary
Clock signal monitoring unit (100), comprising: - a first flip flop (10) and a second flip flop (11), the first flip flop (10) and the second flip flop (11) being cross-coupled, the first flip flop (10) being dockable by a clock signal (CLK) and the second flip flop (11) being clockable by an inverted clock signal (CLK), wherein outputs of the first and second flip flops (10, 11) are connected to a first XOR gate (20); - a third flip flop (12) being dockable by the clock signal (CLK) and a fourth flip flop (13) being dockable by the inverted clock signal (CLK); - an output of the first XOR gate (20) being connected to a delay element (21), the delay element (21) being adapted to delay the output of the first XOR gate (20) to a specified amount of time (T1), wherein the specified amount of time (T1) stands in a defined relationship to a frequency of the clock signal (CLK); - an output of the delay element (21) being connected to the third flip flop (12) and to the fourth flip flop (13); - an output of the third flip flop (12) and an inverted output of the fourth flip flop (13) being connected to the second XOR gate (14); and - an output of the second XOR gate (14) being configured to provide a glitch detect signal (GD).