Clock Enable Filtering for Glitch-Free Clock Generation
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Solution Overview
Problem
Clock generators often produce glitchy clock signals due to glitches in enable signals, which can cause circuits to malfunction or fail, necessitating a solution to generate glitch-free clock signals.
Innovation Solution
A clock generator circuit comprising a clock generating circuit, first and second filter circuits, and an output gate, where the first filter circuit generates a first filtered enable signal based on the duration of the enable signal and the internal clock signal, and the second filter circuit produces a delayed version of the filtered enable signal to ensure the output clock signal is glitch-free.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock generator directly uses the enable signal to generate the output clock signal, then the circuit complexity is low, but the output clock signal contains glitches and is unreliable
Solution Approach 1:
The patent divides the enable signal processing into multiple stages: a first filter circuit that generates a first filtered enable signal, a second filter circuit that generates a second filtered enable signal, and a delay circuit that generates a delayed enable signal. This segmentation allows each circuit to perform a specific filtering function, progressively eliminating glitches while maintaining overall system reliability.
Solution Approach 2:
The patent applies preliminary filtering actions to the enable signal before it reaches the clock generation logic. The first and second filter circuits process the enable signal in advance to remove glitches, and the delay circuit prepares the filtered signal ahead of time. This preliminary action ensures that the clock generation logic receives a clean, glitch-free enable signal, preventing glitch propagation to the output.
2Reliability
If multiple filter circuits are added to filter out glitches, then the output clock signal becomes glitch-free, but the device complexity increases
Solution Approach 1:
The patent introduces intermediate filtered enable signals as mediators between the original enable signal and the clock generation logic. The first filtered enable signal from the first filter circuit and the second filtered enable signal from the second filter circuit serve as intermediate stages that progressively clean the signal. These intermediaries allow complex multi-stage filtering to be implemented in a modular, organized manner that manages overall circuit complexity.
3Reliability
If the enable signal is filtered with multiple stages, then glitches are removed, but the signal processing time increases
Solution Approach 1:
The patent employs periodic clock signals to drive the filter circuits and synchronize the filtering process. The filter circuits operate in sync with the clock periods, processing the enable signal at regular intervals defined by the clock cycles. This periodic operation ensures that filtering is performed systematically without introducing excessive or irregular delays, maintaining timing predictability while achieving glitch removal.
Data Source
AI summary
A clock generator that generates an output clock signal, includes a clock generating circuit that generates an internal clock signal, first and second filter circuits, and an output gate. The first filter circuit receives the internal clock signal and an enable signal, and provides a first filtered enable signal in response to the enable signal having a duration of at least two cycles of the clock signal. The second filter circuit receives the first filtered enable signal, provides a second filtered enable signal in response to the first filtered enable signal, and provides a delayed signal that is a delayed version of the second filtered enable signal. The output gate receives the internal clock signal from the clock generating circuit and the second filtered enable signal from the second filter circuit, and generates the output clock signal.