Clock Enable Throttling for Memory Power Savings

The patent implements dynamic clock gating that adjusts the clock signal state based on memory module activity. When memory modules are idle or in self-refresh mode, the clock signal is gated off to reduce power consumption. When activity is detected, the clock is re-enabled. This dynamic adjustment allows the system to maintain high speeds when needed while reducing power dissipation during idle periods, directly resolving the contradiction between speed and power consumption.

The patent employs periodic clock gating synchronized with memory refresh intervals. The clock signal is periodically disabled during self-refresh operations and re-enabled for normal access operations. This periodic action pattern allows the memory system to maintain high performance during active periods while achieving significant power savings during refresh intervals, effectively managing the speed-power tradeoff.

The patent segments the clock distribution system into individually controllable groups or banks of memory modules. Each segment can have its clock signal independently gated based on its activity state. This segmentation allows the system to support high memory density by adding more modules while consuming power only for the segments that are actively being accessed, rather than powering all modules at full speed continuously.

The patent applies different operational states to different segments of the memory system. Active segments receive full-speed clock signals for high-performance operations, while idle segments have their clocks gated off for minimal power consumption. This local quality approach allows the system to achieve high overall memory density while maintaining low average power consumption by optimizing the operational state of each local segment based on its immediate needs.