Clock Extraction Under Strong Intersymbol Interference
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Solution Overview
Problem
In high-speed optical transmission systems, strong intersymbol interference (ISI) and bandwidth limitations hinder accurate clock extraction, leading to noise enhancement and error multiplication, especially in systems with limited DSP power and complex equalization requirements.
Innovation Solution
A new phase detector and algorithm for setting timing recovery equalizer taps, using (N-1) adders, subtractors, and multipliers to produce symbol outputs, which enables accurate clock tone recovery with low complexity and minimal samples per symbol, stabilizing the timing recovery process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional clock extraction methods are used in bandwidth-limited systems, then the system can operate with simple components, but the clock tone accuracy deteriorates due to strong intersymbol interference
Solution Approach 1:
The patent segments the equalized signal into multiple delayed versions and processes each through separate phase detector paths. By dividing the signal processing into multiple parallel channels with different delay taps, the system can selectively combine components that are less affected by ISI, thereby improving clock tone accuracy in bandwidth-limited systems.
Solution Approach 2:
The patent introduces an intermediary timing recovery equalizer that processes the signal before the main equalizer. This intermediary equalizer acts as a mediator to pre-condition the signal, reducing the impact of strong ISI on subsequent clock extraction operations and enabling more accurate timing recovery.
2Measurement precision
If complex equalization is applied to combat ISI, then clock extraction accuracy improves, but DSP power consumption increases
Solution Approach 1:
The patent divides the equalization function into two separate equalizers: a timing recovery equalizer with fewer taps dedicated to clock extraction, and a main equalizer for data recovery. This segmentation allows the system to achieve accurate clock extraction with lower computational complexity in the timing-specific equalizer, reducing overall DSP power consumption while maintaining clock extraction accuracy.
Solution Approach 2:
The patent applies partial equalization specifically targeted at timing recovery needs rather than full equalization for all signal processing purposes. The timing recovery equalizer uses a limited number of taps (e.g., 3-7 taps) sufficient for clock extraction, avoiding the excessive computational burden of full-spectrum equalization while achieving the necessary clock tone accuracy.
3Stability of the object's composition
If more samples per symbol are used for timing recovery, then clock tone stability improves, but processing complexity and latency increase
Solution Approach 1:
The patent processes signals in segmented blocks of N symbols at a time through parallel phase detectors. This block-based segmentation allows the system to achieve timing stability through accumulated processing of multiple symbols while maintaining manageable computational complexity through efficient parallel implementation and reusable processing structures.
Data Source
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AI summary
Timing recovery apparatus for signal reception in a data transmission system, comprises an equalizer to equalize a received signal and a phase detector connected after the timing recovery equalizer that generates a clock tone from absolute values of the received signal after equalization.