Synchronisation Error Detection TRIZ Cases
- PPM Frequency Offset Detection Without a Third Reference Clock
Counter-based detection compares two asynchronous clock signals to find frequency offset while cutting reference-clock circuitry and power use.
- Differential Driver Timing Control for Multi-Level Noise Suppression
Dynamic timing adjustment by transition state helps multi-level differential drivers suppress common mode noise and improve communication performance.
- Multi-Level Differential Driver Timing for Common-Mode Noise
Transition-specific timing adjustment in a differential driver cuts common-mode noise in multi-level signaling and helps reduce EMI.
- DFE Tap Circuit With Common-Mode Reset for Faster SERDES
A current integrating summer resets output nodes to common mode, letting DFE taps carry signal current only for faster, lower-power SERDES.