Decision Feedback Equalizer Phase Swapping for Data Rate Adaptation
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Solution Overview
Problem
Decision Feedback Equalization (DFE) circuits in high-speed serial links face limitations due to delay issues, which are exacerbated in wide-band serial links, making it challenging to simultaneously satisfy the set-up time for high data rates and hold-time for low data rates without introducing additional delay in the DFE path.
Innovation Solution
A method and apparatus that utilize a selection circuit block to swap phases and corresponding equalized sample streams of a clock signal responsive to data rates, allowing for efficient operation at both high and low data rates without additional delay in the DFE path, using a decision feedback equalizer and a phase interpolator to adjust clock signal phases and sample streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DFE circuitry is used to improve bit error rate, then reliability is improved, but delay increases which limits frequency of operation
Solution Approach 1:
The DFE circuit is divided into multiple independent feedback paths, each handling specific delay requirements. This segmentation allows different parts of the circuit to operate at different speeds, enabling the overall system to achieve both high reliability through comprehensive equalization and high speed through optimized critical path timing.
2Adaptability or versatility
If additional delay is introduced in DFE path to satisfy hold-time for low data rates, then adaptability is improved, but frequency of operation decreases
Solution Approach 1:
The circuit employs dynamic phase selection where the clock phase applied to sampling elements is switched based on the current data rate. At high data rates, one phase configuration satisfies set-up time requirements, while at low data rates, a different phase configuration satisfies hold-time requirements. This dynamic adaptation allows the circuit to maintain optimal timing margins across the full data rate range without introducing fixed additional delay.
3Speed
If set-up time parameter is optimized for high data rate, then speed is improved, but hold-time parameter is not satisfied for low data rate
Solution Approach 1:
The circuit dynamically switches between different clock phases based on operating conditions. For high data rates, the circuit uses a phase configuration that optimizes set-up time, allowing maximum speed operation. For low data rates, it switches to a different phase configuration that ensures hold-time requirements are met. This dynamic phase switching enables the circuit to satisfy both timing parameters across the full data rate range.
Solution Approach 2:
The circuit changes the effective timing parameters by switching clock phases. By altering which clock phase is used for sampling, the circuit effectively changes the timing relationships between data arrival and sampling events. This parameter change allows optimization of set-up time at high data rates while ensuring hold-time satisfaction at low data rates, without requiring fixed circuit modifications.
Data Source
AI summary
A method relates generally to data reception for any of a plurality of data rates. In such a method, information and phases of a clock signal are obtained by a decision feedback equalizer. The information is equalized using the phases of the clock signal with the decision feedback equalizer to provide equalized sample streams. The equalized sample streams and the phases of the clock signal are provided to a selection circuit block. A first and a second phase of the phases are swapped, along with swapping a first and a second equalized sample stream corresponding to the first phase and the second phase, responsive to a data rate of the plurality of data rates.