Data Recovery Circuit Dynamic Edge Adjustment
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Solution Overview
Problem
Existing data recovery circuits require a communication rate that is an integer multiple of the frequency of parallel data output by the oversampling circuit, limiting the maximum oversampling frequency and precision, especially in ASICs and FPGAs, and necessitating lengthy development periods for different communication frequencies.
Innovation Solution
A data recovery circuit that includes an oversampling unit, edge detection unit, edge position calculation unit, phase comparison unit, and data sampling unit, allowing for the estimation and adjustment of edge positions in parallel data to enable maximum oversampling clock frequency independent of serial data communication rate, using high-speed communication IP cores for efficient operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the communication rate is set to an integer multiple of the parallel data frequency in conventional oversampling circuits, then the circuit operation is simplified, but the maximum oversampling frequency is limited and precision is reduced
Solution Approach 1:
The patent introduces a dynamic edge position adjustment mechanism that adapts the sampling timing based on detected edge positions. The circuit dynamically calculates and adjusts the sampling clock phase to optimally sample parallel data edges, enabling high-precision data recovery without requiring the communication rate to be an integer multiple of the parallel data frequency. This dynamic adaptation resolves the contradiction by making the system flexible rather than fixed.
Solution Approach 2:
The patent implements a feedback loop where the edge detection unit detects actual edge positions of parallel data, compares them with expected positions, and uses this information to adjust the sampling timing. The phase comparison unit continuously monitors the difference between detected and expected edge positions, and the edge position adjustment unit modifies the sampling clock phase accordingly. This feedback mechanism enables the circuit to maintain high precision regardless of the relationship between communication rate and parallel data frequency.
2Measurement precision
If the oversampling frequency is increased to improve precision, then data recovery accuracy improves, but the development period increases when using dedicated ASIC designs for different communication frequencies
Solution Approach 1:
The patent creates a universal data recovery circuit that can operate at various oversampling frequencies and adapt to different communication rates through software or configuration parameters rather than hardware redesign. The edge position adjustment mechanism and phase comparison unit are designed to be frequency-agnostic, allowing the same circuit architecture to be used across different applications and communication standards, thereby reducing development time while maintaining high precision.
Solution Approach 2:
The patent enables flexible parameter configuration where the oversampling frequency, parallel data width, and sampling timing can be adjusted through control parameters rather than fixed hardware design. This allows the same circuit to be optimized for different communication rates and applications by changing parameters such as the oversampling ratio and edge position offset, eliminating the need for lengthy redesign cycles for each new application.
3Measurement precision
If the number of oversampling times is increased to maximize precision, then sampling position adjustment becomes finer, but the constraint that communication rate must be an integer multiple of parallel data frequency limits the usable oversampling frequencies
Solution Approach 1:
The patent introduces dynamic edge position adjustment that allows the sampling timing to be flexibly adapted to any oversampling frequency, not just those that are integer multiples of the parallel data frequency. The circuit dynamically calculates the optimal sampling position based on detected edge positions and adjusts the sampling clock phase accordingly, enabling fine sampling position adjustment across a wide range of oversampling frequencies.
Solution Approach 2:
The patent adds a new dimension of control by introducing edge position offset parameters that independently adjust the sampling timing relative to the parallel data edges. This additional degree of freedom allows the circuit to achieve precise sampling positions even when the oversampling frequency is not an integer multiple of the parallel data frequency, effectively decoupling the sampling precision from the frequency relationship constraint.
Data Source
AI summary
In a data recovery circuit, the position of an edge is detected from parallel data acquired by oversampling data received through serial communication, the position of a next edge is estimated, the estimated position of the edge is compared with the detected position of the actual edge, and the sampling position of the parallel data is adjusted based on a result of the comparison. As a result, an oversampling clock can be set to a maximum frequency, and accordingly, the precision of the data recovery circuit can be improved.