DFE Tap Circuit With Common-Mode Reset for Faster SERDES
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Solution Overview
Problem
High data rate serializer deserializer (SERDES) devices face challenges in achieving fast data rates without compromising power efficiency, as driving decision feedback equalization (DFE) taps with more power increases power consumption and requires large devices to handle both signal and common mode currents, limiting operational speed and efficiency.
Innovation Solution
Implementing current integrating summers that reset to a common mode voltage potential instead of power supply voltage potential, allowing DFE taps to carry only signal current and reducing the size and power consumption of devices, thereby enhancing operational speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DFE taps are driven with more power to achieve fast data rates, then operational speed is improved, but power consumption increases
Solution Approach 1:
The patent segments the current path by introducing a dedicated common mode voltage potential node that is electrically isolated from the power supply voltage node. This segmentation allows signal current to flow through the DFE tap devices while common mode current is directed through a separate path, enabling devices to be sized for signal current only and reducing power consumption while maintaining fast operational speed.
Solution Approach 2:
The patent introduces a common mode voltage potential node as an intermediary element between the power supply and the DFE tap output nodes. This intermediary node serves as a dedicated return path for common mode current, preventing it from flowing through the signal path devices. As a result, devices can operate at high speed with reduced power consumption since they only handle signal current.
2Reliability
If devices are sized to handle both signal and common mode currents, then reliability is improved, but device size increases
Solution Approach 1:
The patent segments the current paths by creating a separate common mode voltage potential node, allowing DFE tap devices to be sized for signal current only while a separate path handles common mode current. This maintains reliability by providing dedicated paths for each current type while reducing device size.
Solution Approach 2:
The common mode voltage potential node acts as an intermediary that provides a dedicated return path for common mode current. This allows signal path devices to be smaller since they only need to handle signal current, while reliability is maintained through the separate common mode current path.
3Strength
If devices are sized to handle both signal and common mode currents, then device robustness is improved, but operational speed decreases
Solution Approach 1:
The patent segments current paths by introducing a separate common mode voltage potential node, allowing devices to be optimized for signal current handling speed while a separate path manages common mode current. This segmentation enables faster operational speed by removing the burden of switching large common mode currents from the signal path devices.
Solution Approach 2:
The common mode voltage potential node serves as an intermediary that provides a dedicated path for common mode current, allowing signal path devices to be smaller and faster. Device robustness is maintained through the separate common mode path while operational speed is improved by eliminating common mode current switching requirements from the signal path.
Data Source
AI summary
Decision feedback equalization (DFE) tap systems and related apparatuses and methods are disclosed. An apparatus includes output nodes to provide output signals, a complementary metal-oxide-semiconductor (CMOS) DFE tap electrically connected to the output nodes, and a current integrating summer electrically connected to the output nodes. The current integrating summer is to reset the output nodes to a common mode voltage potential.