Dynamic Latency-Based Fabric Multipathing
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Solution Overview
Problem
Existing data center and telecom networks face challenges in providing low latency paths due to varying latency across different Ethernet ports and paths, despite configured path cost factors, which affects service availability and redundancy.
Innovation Solution
A system that synchronizes clocks across multiple link aggregation (LAG) ports and paths using Precision Time Protocol (PTP), determines latency for each LAG port and path, and marks the lowest latency paths for preferential use by traffic demanding low latency, ensuring efficient packet forwarding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If path cost factor is configured based on highest speed or available bandwidth, then network bandwidth utilization is improved, but actual latency varies dramatically across paths with same path cost factor
Solution Approach 1:
The patent applies dynamics by transitioning from static path cost factors to dynamic latency measurements. The system continuously discovers and updates latency values for multiple paths between device pairs, allowing the multipath algorithm to adaptively select paths based on current latency conditions rather than fixed bandwidth-based costs. This enables the network to dynamically respond to changing latency conditions while maintaining high bandwidth utilization.
Solution Approach 2:
The patent changes the parameter used for path selection from path cost factor (bandwidth-based) to measured latency. By introducing latency as a new parameter and using it to mark preferred paths in the multipath algorithm, the system directly addresses the latency variation problem while preserving the benefits of multiple path utilization for bandwidth efficiency.
2Ease of operation
If multipath algorithm relies on path cost factor, then routing decisions are simplified, but latency optimization is compromised due to equal cost paths having different actual latencies
Solution Approach 1:
The patent applies preliminary action by pre-discovering and storing latency values for all possible paths between device pairs before routing decisions are made. The latency discovery process proactively measures and caches path characteristics, so when routing decisions are needed, the system can quickly consult pre-computed latency information rather than performing complex real-time measurements, thus maintaining simplicity while optimizing for latency.
3Measurement precision
If clock synchronization is performed across multiple LAG ports independently, then latency measurement accuracy is improved, but system complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the clock synchronization process into independent per-LAG-port operations. Each LAG port undergoes separate latency discovery and clock synchronization, allowing the system to measure and record latency for each individual port independently. This segmentation enables accurate per-port latency measurement while the modular nature of the process keeps implementation complexity manageable through reuse of standard PTP mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a highly available and low latency path selection mechanism, enhancing network performance by dynamically determining and utilizing the lowest latency paths, even in scenarios with equal cost multipathing, thereby improving service reliability and efficiency.
Implementation Method 1
transit delay is precisely calculated using a PTP delay request packet which is sent and received by a device. This transit delay is precisely equal to the latency of the path traversed by the PTP delay_request packet.
Data Source
AI summary
In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith, the program instructions being executable by a processor to cause the processor to determine a lowest latency LAG port for each LAG in any path of a plurality of paths connecting a first device with a second device, and discover a configuration of a network fabric connecting the first device to the second device after determining the lowest latency LAG port for each LAG therein. The network fabric includes a plurality of devices interconnected with LAGs. Moreover, the embodied program instructions are executable by the processor to perform clock synchronization for each path of the plurality of paths and determine a latency for each path of the plurality of paths based on the clock synchronization and the lowest latency LAG port for each LAG included in the plurality of paths.