Clock Recovery Using Tap Coefficient Imbalance in Optical Receivers
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Solution Overview
Problem
Conventional clock recovery schemes in coherent optical receivers fail to operate reliably in highly distorted signal conditions and consume excessive power, particularly in high-speed optical transmission systems.
Innovation Solution
A clock recovery apparatus using an adaptive multi-tap filter with four tapped delay lines, where tap coefficients are determined using algorithms like the Constant Modulus Algorithm (CMA) to control the frequency of the local clock signal, balancing precursor and postcursor tap coefficients to adjust the clock frequency, thereby enabling distortion-tolerant and power-efficient clock recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional digital clock recovery schemes based on oversampling are used, then distortion tolerance is improved, but power consumption increases
Solution Approach 1:
The patent extracts only the essential information needed for clock recovery from the received signal by using tap coefficients from the equalizer, rather than processing the entire oversampled signal. This selective extraction maintains distortion tolerance while significantly reducing computational complexity and power consumption.
Solution Approach 2:
The patent makes the equalizer tap coefficients serve dual purposes: both for signal equalization and for clock recovery. By utilizing the existing equalizer coefficients for both functions, the system avoids separate processing stages, thereby reducing overall power consumption while maintaining reliable clock synchronization under distorted conditions.
2Use of energy by moving object
If standard analog clock recovery schemes are used, then power consumption is reduced, but they fail to operate reliably in highly distorted signal conditions
Solution Approach 1:
The patent introduces digital signal processing of equalizer tap coefficients as an intermediary step between the distorted received signal and the clock recovery decision. This digital intermediary processing extracts meaningful timing information even from highly distorted signals, enabling reliable clock recovery without requiring high power consumption analog circuits.
3Reliability
If high processing power is used for digital clock recovery, then distortion tolerance is improved, but device complexity increases
Solution Approach 1:
The patent extracts clock recovery information directly from the equalizer tap coefficients without requiring additional complex digital processing stages. By taking out only the necessary timing information from existing processing results, the system achieves distortion tolerance while minimizing device complexity.
Data Source
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AI summary
The invention relates to a clock recovery apparatus for use in an optical receiver. The receiver comprises electrical means (11a-d) clocked by a clock signal for sampling a received signal and an adaptive multi-tap filter connected downstream of the means (11a-d) and receiving adjustable tap coefficients. The clock recovery apparatus comprises comparison means (16) for comparing precursor and postcursor tap coefficients. Usually, when the clock is locked to the received signal, precursor and postcursor tap coefficients are more or less balanced. However, if the clock is not locked, the coefficients become unbalanced. Such imbalance is determined by the comparison means (16) and the information is used for controlling the frequency of the clock signal as generated by clock generation means (12, 13).