IEEE 1394 Reception Port Clock Synchronization and Data Shaping
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Solution Overview
Problem
Conventional semiconductor devices for receiving packet data based on the IEEE 1394 standard face issues with decoding time variability due to differing clock frequencies, leading to potential data dropout errors when synchronizing and shaping data, especially when the reception clock signal frequency is lower than the internal clock signal frequency.
Innovation Solution
A semiconductor device with a synchronization memory that synchronizes reception data with an internal clock signal, a decoder for decoding the data, and a shaping memory with a storage determination circuit to manage data storage based on standardized and non-standardized lengths, ensuring fixed timing output and preventing dropout errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the decoder decodes reception data in response to the reception clock signal, then the decoding process can be completed, but the decoding time is lengthened when the reception clock frequency is lower than the internal clock frequency
Solution Approach 1:
The patent applies preliminary action by performing synchronization of reception data with the internal clock signal before the decoding process. The synchronization unit aligns the reception data timing with the internal clock in advance, so that subsequent decoding operations can proceed at the higher internal clock frequency without timing conflicts, thereby reducing overall decoding time while ensuring reliable completion
Solution Approach 2:
The patent introduces a synchronization unit as an intermediary component between the reception data (synchronized with reception clock) and the decoder (operating with internal clock). This mediator translates and aligns timing between the two different clock domains, enabling the decoder to operate at its optimal internal clock frequency while processing reception data that arrives at a different rate
2Reliability
If the synchronization-shaping FIFO memory stores reception data, then data synchronization and shaping can be performed, but data dropout errors occur when storage timing deviates from output timing
Solution Approach 1:
The patent applies preliminary action by performing synchronization of reception data with the internal clock signal before the decoding process. The synchronization unit aligns the reception data timing with the internal clock in advance, so that subsequent decoding operations can proceed at the higher internal clock frequency without timing conflicts, thereby reducing overall decoding time while ensuring reliable completion
Solution Approach 2:
The patent introduces a synchronization unit as an intermediary component between the reception data (synchronized with reception clock) and the decoder (operating with internal clock). This mediator translates and aligns timing between the two different clock domains, enabling the decoder to operate at its optimal internal clock frequency while processing reception data that arrives at a different rate
Data Source
AI summary
An improved reception port for receiving packet data based on the IEEE 1394 standard. The reception port includes a synchronization FIFO memory for receiving reception data in accordance with a reception clock signal and synchronizing the reception data with an internal clock signal, a decoder for decoding the synchronized reception data, and a shaping FIFO memory for outputting the decoded reception data at a fixed timing.