Clock-Filtered Data Receiver for Jitter-Correlated Signal Recovery
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Solution Overview
Problem
High-speed and low-power transceiver systems face challenges with clock signal jitter amplification, uncorrelated jitter generation in clock distribution networks, and latency mismatch between data and clock signals, which affect the correlation between data and clock signals, leading to increased power consumption and noise-induced jitter.
Innovation Solution
A data signal receiver is designed with a clock signal filter, falling pulse signal generator, and sampler to remove high-frequency jitter components from the clock signal, mixing it with the data signal to generate a recovered data signal that highly correlates with low-frequency clock signal jitter, thereby reducing medium and high-frequency jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If latency removing method is used to add latency to data signal, then latency difference between data signal and clock signal is reduced, but power noise induced jitter occurs and power consumption increases
Solution Approach 1:
The patent extracts and removes high-frequency jitter components from the clock signal using a clock signal filter before mixing it with the data signal. This extraction approach eliminates the need for adding latency to the data signal, thereby avoiding the power consumption penalty associated with the latency removing method while still achieving jitter correlation enhancement.
Solution Approach 2:
The patent introduces a clock signal filter as an intermediary component that processes the clock signal before it is mixed with the data signal. This intermediary filter removes high-frequency jitter components, enabling jitter correlation improvement without requiring latency addition to the data signal path, thus avoiding the associated power consumption increase.
2Use of energy by stationary object
If clock signal jitter filtering method is used to filter high frequency jitter component, then implementation is easier and power consumption is reduced, but not all high frequency jitter components are removed and phase noise is replaced
Solution Approach 1:
The patent creates a filtered version of the clock signal that contains only the desired low-frequency jitter components by using a clock signal filter. This filtered clock signal is then mixed with the data signal to produce a recovered data signal with enhanced jitter correlation, achieving effective jitter filtering without requiring complete removal of all high-frequency components.
3Device complexity
If embedded-clock architecture is used to transfer only data signal, then clock channel is not required, but CDR circuit increases power consumption and execution time
Solution Approach 1:
The patent merges the clock signal and data signal processing into a single mixing operation. By filtering the clock signal and mixing it with the data signal, the system recovers the clock signal embedded in the data signal without requiring a separate CDR circuit, thereby reducing power consumption while maintaining the embedded-clock architecture's channel structure advantage.
Data Source
AI summary
A data signal receiver includes a clock signal filter, a falling pulse signal generator, a mixing block, and a sampler. The clock signal filter generates a first filtered clock signal and a second filtered clock signal by filtering a clock signal. The falling pulse signal generator generates a falling pulse signal based on the first filtered clock signal. The mixing block generates a mixed data signal by mixing a data signal and the falling pulse signal. The sampler generates a recovered data signal by sampling the mixed data signal in response to the second filtered clock signal.