Pulse Manipulation TRIZ Cases
- Interrupt Debouncing with Noise Filtering for Mechanical Switch Signals
Timed masking and stability checks filter switch bounce before raising interrupts, improving accuracy while reducing CPU load.
- MOS Voltage Selection Circuit for Low-Drop Terminal Protection
MOS transistor switching selects the highest or lowest terminal voltage to block parasitic diode current, reducing drop, heat, and overcurrent.
- Glitch Filter Circuit for Low-Delay Edge and Logic Stability
Separate pull-up and pull-down control paths filter high and low glitches while reducing edge delay and preventing false output toggles.
- Clock-Filtered Data Receiver for Jitter-Correlated Signal Recovery
Filtering high-frequency clock jitter before pulse mixing improves data-clock correlation, cutting noise-induced jitter and power use.
- Phase Interpolation Circuit for Linear Clock Phase at High Bit Rates
Weighted mixing of phased reference clocks improves clock phase linearity in CDR receivers without adding more complex phase paths.
- Configurable Delay Element With Glitch-Less Low-Power Phase Shifting
Segmented delay chains and timed code updates cut buffer power use while preventing glitches and data corruption during phase shifts.
- Programmable Delay Circuit With PVT-Compensated RC Timing
Threshold-dependent capacitance and triggering cancel process variation, giving programmable delay with better linearity and noise tolerance.
- Dual-Rail Delay Chain for Precise Voltage-to-Time Conversion
Large cross-coupled inverters in a dual-rail delay chain improve voltage measurement precision and reduce metastability in digital regulators.
- Cascaded CMOS Phase Interpolator for Precise Clock Phase Generation
A cascaded CMOS interpolator generates precise equidistant clock phases with fewer coarse DLL phases, reducing skew and hardware complexity.
- Transmitter Output Impedance Calibration for Rise-Fall Time Equalization
Closed-loop PMOS/NMOS ratio tuning equalizes transmitter rise and fall times to cut jitter, EMI, and signal asymmetry.
- Symmetric Digital Delay Circuit for Threshold-Independent Timing
Two matched delay stages with equal source and sink currents cancel threshold-voltage shifts, keeping timing stable across process and temperature changes.
- Direct Digital Frequency Synthesis Without Off-Chip Filters
An accumulator-driven pulse stream removes off-chip filters and high-resolution DAC demands, cutting DDS size, cost, and clock artifacts.
- Configurable Digital Delay Line With Glitch-Free Path Switching
Tri-state inverter lattices let delay cells receive live data before switching, enabling variable digital delay without signal glitches.
- Programmable Delay Circuit With PVT-Compensated Threshold Tracking
Voltage-dependent capacitance and trigger thresholds offset PVT variation, enabling programmable delay with better linearity and noise immunity.
- Sensorless Motor Driving Device BEMF Detection
A motor driving device detects back electromotive force using a floating point selecting unit and control unit.