Programmable Delay Circuit With PVT-Compensated Threshold Tracking
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Solution Overview
Problem
Existing delay circuits are sensitive to process, voltage, and temperature variations, leading to significant differential nonlinearity and impracticality in modern chip and system designs.
Innovation Solution
A delay circuit design that incorporates a capacitor with a threshold voltage-dependent capacitance and a triggering circuit, where the capacitance and triggering voltage changes inversely to cancel out process variations, along with multiple triggering circuits and a programmable delay mechanism using a variable current source, to reduce sensitivity to process variations and improve noise immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a standard inverter delay cell is used, then the circuit is simple to implement, but the delay variation is very sensitive to process, power supply voltage and ambient temperature variations (variation on the order of 50%)
Solution Approach 1:
The patent changes the parameters of the delay cell by using a capacitor with voltage-dependent capacitance and a triggering circuit with voltage-dependent threshold. The capacitance C(V) decreases as voltage increases, and the triggering threshold Vth also varies with voltage. These parameter changes cause the delay to be less sensitive to PVT variations because the voltage-dependent effects compensate for each other, reducing the overall variation from 50% to a much smaller range.
2Reliability
If modified inverter delay cells with constant current or self-biased current generators are used, then delay variation based on process is reduced, but the circuit complexity increases and calibration is required
Solution Approach 1:
The patent applies self-service by using a capacitor whose capacitance automatically adjusts based on its voltage state, and a triggering circuit whose threshold automatically adjusts based on voltage. This self-adjusting mechanism eliminates the need for external calibration circuits or complex current generators, achieving delay variation reduction without increasing circuit complexity or requiring calibration procedures.
3Duration of action of moving object
If multiple cascaded delay cells are used to increase delay step, then the required delay time is achieved, but the delay step linearity worsens due to accumulation of delay error
Solution Approach 1:
The patent applies dynamics by making the capacitance and triggering threshold voltage-dependent rather than fixed. This dynamic behavior allows the delay cell to maintain consistent timing characteristics across different operating conditions and delay steps. The voltage-dependent parameters automatically adjust to compensate for errors, preserving delay step linearity even when multiple cells are cascaded to achieve longer delay times.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed delay circuit achieves reduced sensitivity to process variations, temperature, and power supply variations, maintaining consistent time delay across different fabrication processes and improving noise immunity.
Implementation Method 1
The capacitor may have a threshold voltage, with the capacitance of the capacitor being dependent, at least in part, on the threshold voltage
Implementation Method 2
the capacitance of the capacitor being dependent, at least in part, on the threshold voltage. For example, the capacitor may include a first transistor, such as a MOS transistor
Implementation Method 3
the triggering circuit may include a second transistor with the same threshold voltage as the first transistor used for the capacitor
Data Source
AI summary
A delay circuit is described having a variable capacitor and a triggering circuit. The variable capacitor and the triggering circuit may both comprise transistors. With both the variable capacitor and the triggering circuit dependent on the threshold voltage, the delay circuit may be less sensitive to process variations. The delay circuit may also include a capacitor, a first triggering circuit, a second triggering circuit, and a pull down circuit. The capacitor may discharge at a first rate, triggering the first triggering circuit which, in turn, activates the pull down circuit to pull down the capacitor at a second rate that is faster than the first rate. The second triggering circuit is triggered as the capacitor is pulled down, thereby reducing the effect of input signal noise on the output of the delay circuit. The discharging of the capacitor may be adjusted by a control input thereby making the delay of the delay circuit programmable.