Symmetric Digital Delay Circuit for Threshold-Independent Timing
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Solution Overview
Problem
Prior art digital delay circuits experience varying time delays due to dependence on the logic threshold voltage, which is affected by manufacturing process variations and temperature changes.
Innovation Solution
A digital delay circuit design featuring two identical delay stages with capacitors and switched current sources, where the sourcing and sinking currents are equal in magnitude, and digital circuits with identical threshold voltage levels, ensuring the time delay is independent of the threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single delay circuit with a capacitor and switched current source is used, then the circuit structure is simple, but the time delay varies with threshold voltage changes due to process variations and temperature effects
Solution Approach 1:
The delay circuit is divided into two identical delay stages connected in cascade. Each stage consists of a capacitor and switched current sources. By segmenting the circuit into two symmetric stages, the threshold voltage variations affect both stages equally, and their effects cancel out in the overall delay time, thereby stabilizing the time delay against process and temperature variations.
2Device complexity
If the delay circuit uses a single stage with capacitor charging/discharging, then the circuit is simple, but the time delay is directly dependent on the threshold voltage level which varies with temperature and process
Solution Approach 1:
The patent employs symmetric asymmetry by using two identical delay stages with opposite polarity switching. The first stage charges the capacitor while the second stage discharges it, or vice versa. This symmetric configuration ensures that threshold voltage variations, which are inherent to digital circuits, affect both stages equally and thus cancel out in the total delay calculation, achieving threshold voltage independence.
Solution Approach 2:
The patent changes the operational parameters by using equal magnitude sourcing and sinking current sources in each delay stage. This parameter configuration ensures that the charging and discharging times are equal, and when combined with the symmetric two-stage structure, the threshold voltage effects are eliminated from the overall delay expression, making the delay stable against process and temperature variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design provides a consistent time delay that is not influenced by threshold voltage variations, stabilizing the delay across different manufacturing processes and temperature conditions.
Implementation Method 1
The first delay circuit comprises a first capacitor, first and second switched current sources each coupled to the first capacitor
Data Source
AI summary
A digital time delay circuit is provided in which fabrication process variations and temperature effects on the switching threshold level of digital circuits utilized in the timing delay circuits are substantially eliminated.