Cascaded CMOS Phase Interpolator for Precise Clock Phase Generation
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Solution Overview
Problem
Current phase rotators using CMOS signaling face challenges in achieving high precision and efficiency due to non-uniform topology and the need for a large number of coarse clock phases, leading to skew issues and increased hardware requirements.
Innovation Solution
A novel all-CMOS phase rotator architecture that merges phase generation and selection into a uniform array of delay and switching elements, utilizing vernier topology and a cascade of identical single-bit sections for interpolation, reducing hardware needs and improving linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large number of coarse clock phases are generated using a Delay Locked Loop (DLL), then the phase coverage is improved, but the circuit complexity and skew control difficulty increase
Solution Approach 1:
The phase generation is divided into two independent stages: a coarse phase generator using DLL that provides a limited set of uniformly distributed phases, and a fine interpolator that generates additional phases by interpolating between adjacent coarse phases. This segmentation allows the DLL to handle only the essential phase coverage while the interpolator handles the fine-grained phase generation, reducing the overall circuit complexity and skew control difficulty.
Solution Approach 2:
The fine interpolator is nested within the overall phase generation system, taking the output of the coarse phase generator as its input. The interpolator is further divided into multiple cascaded stages, where each stage interpolates between phases generated by the previous stage, creating a hierarchical nested structure that efficiently expands phase coverage without proportionally increasing complexity.
2Measurement precision
If current-mode logic (CML) mixers are used for interpolation, then linearity is improved, but compatibility with CMOS circuits deteriorates
Solution Approach 1:
The patent replaces the CML mixer-based interpolation mechanism with a CMOS-compatible digital logic-based interpolator. Instead of using analog current-mode mixing, the invention uses digital logic circuits (AND gates, OR gates, and buffers) to generate interpolated phases by combining coarse phases according to binary-weighted control signals. This substitution maintains adequate linearity for clock generation applications while achieving full CMOS compatibility.
3Adaptability or versatility
If tri-state inverters are used for CMOS-compatible interpolation, then CMOS compatibility is improved, but linearity deteriorates
Solution Approach 1:
The patent employs dynamic control of the interpolator stages using binary-weighted control signals that change over time. Each interpolator stage is dynamically switched between different operational states based on the control signals, allowing the circuit to adapt its behavior to maintain linearity. The cascaded structure dynamically propagates phases through multiple stages, with each stage contributing to the final interpolated phase in a controlled manner that improves linearity compared to simple tri-state inverter approaches.
4Measurement precision
If interpolation accuracy is increased by adding more tri-state inverters, then precision is improved, but hardware requirements double with each extra bit
Solution Approach 1:
The interpolation process is segmented into multiple cascaded stages, where each stage handles a portion of the interpolation task. Instead of using a single large array of tri-state inverters, the patent divides the interpolation into sequential steps, with each stage using a manageable number of logic gates. This segmentation allows high precision to be achieved without requiring an exponential increase in hardware, as each stage contributes additively to the overall precision.
Solution Approach 2:
The patent replaces the tri-state inverter-based interpolation mechanism with a digital logic-based approach using AND gates, OR gates, and buffers. This substitution dramatically reduces the hardware requirements for achieving the same interpolation accuracy. The digital logic circuits can be efficiently implemented in CMOS technology and scale linearly with precision requirements rather than exponentially, as the logic gates can be reused and cascaded in a systematic manner.
5Measurement precision
If coarse phases are selected from a large set, then phase resolution is improved, but skew control becomes more difficult
Solution Approach 1:
The phase generation is segmented into coarse and fine components. The coarse phase generator using DLL provides a limited set of uniformly distributed phases with well-controlled skew, while the fine interpolator generates additional phases by interpolating between adjacent coarse phases. This segmentation ensures that the coarse phases, which are the primary source of skew, are kept in a manageable number, while the fine phases inherit the skew characteristics of their parent coarse phases plus a small additional interpolation error, maintaining overall skew control.
Solution Approach 2:
The fine interpolator is nested within the overall phase generation system, taking the output of the coarse phase generator as its input. The interpolator is further divided into multiple cascaded stages, where each stage interpolates between phases generated by the previous stage, creating a hierarchical nested structure. This nesting allows the fine phases to inherit the timing characteristics of the coarse phases while adding fine-grained resolution, thereby improving phase resolution without proportionally increasing skew control difficulty.
Data Source
AI summary
A programmable delay generator and a cascaded interpolator are provided. The cascaded interpolator includes a set of interpolator stages, each having two signal inputs and two signal outputs, configured to receive two input signals having two different phases and to generate two output signals that have a phase separation equal to a fraction of a phase separation of the two input signals; and a phase converter connected to a last stage of the plurality of single-bit interpolator stages, configured to convert the two output signals into a single final output signal of a given phase.