Dual-Rail Delay Chain for Precise Voltage-to-Time Conversion

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Solution Overview

Problem

Conventional voltage-to-time conversion techniques in integrated circuits suffer from low precision and inefficiency due to the inability to accurately measure power supply voltage, leading to improper operation or unnecessary halting of circuits.

Innovation Solution

A digital voltage regulator using a dual rail delay chain with cross-coupled inverters of larger size, which enhances resolution and reduces metastability, allowing for precise power supply voltage measurement by propagating signals through a delay chain with sub-fan-out one stage delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional inverter chains are used for voltage-to-time conversion, then the device complexity is low, but the measurement precision is insufficient

Engineering Contradiction:
Improvevoltage measurement precisionVSAvoiddelay chain complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The delay chain is segmented into multiple fine-grained stages with individual sampling points between inverters, allowing precise measurement of voltage-induced delay variations. Each stage contributes to the overall delay measurement, enabling high-resolution voltage-to-time conversion through cumulative timing data from segmented sections.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from single-rail delay measurement to dual-rail differential measurement by introducing complementary delay chains. This dimensional expansion allows simultaneous measurement of rise and fall delays, doubling the information content and precision of voltage measurements while maintaining comparable device complexity through symmetric architecture.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If standard flip-flops with internal data complement generation are used, then the device complexity is low, but the metastability window is large causing measurement errors

Engineering Contradiction:
Improvesampling accuracyVSAvoidflip-flop structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The data complement signal is generated in advance through the dual-rail delay chain architecture rather than internally within the flip-flop. This preliminary generation of complementary signals eliminates the metastability issue by ensuring both data and complement signals are stable before sampling, improving measurement accuracy without requiring complex internal flip-flop structures.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If voltage-to-time conversion is performed with low precision, then the device complexity is low, but the operating efficiency decreases due to unnecessary circuit halting

Engineering Contradiction:
Improvecircuit operating efficiencyVSAvoidvoltage measurement precision
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The delay chain measurement system provides feedback about power supply voltage conditions to control logic that manages circuit operation. By continuously monitoring voltage through precise delay measurements and comparing against threshold values, the system can make informed decisions about when to halt or continue circuit operation, maximizing productivity by avoiding unnecessary halts while maintaining voltage safety margins.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8198931B2Fine grain timing
Publication Date: 2012.06.12 ORACLE AMERICAN INC
  • US8198931B2 patent drawing
  • US8198931B2 patent drawing
  • US8198931B2 patent drawing

AI summary

A dual rail delay chain having cross-coupled inverters that interconnect the two rails. Delay chain embodiments include cross-coupled inverters that are part of a feed forward signal path between the two rails and are of a larger size than inverters associated with the two rails. The large size feed forward cross-coupled inverters contribute to an enhanced resolution of the delay chain.