Configurable Digital Delay Line With Glitch-Free Path Switching
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Solution Overview
Problem
NAND gate-based digital delay lines experience signal inconsistencies and glitches when delay cells are enabled or disabled, as they do not store signal information, leading to unpredictable signal propagation.
Innovation Solution
A configurable delay line system using a lattice of delay cells with tri-state inverters, where control signals dynamically adjust the number of delay cells in the signal path, ensuring that each cell receives live data before being added, preventing glitches by using high and low active control tri-state inverters to manage signal propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If NAND gates are used as delay cells in a lattice configuration, then the delay line can be configured to provide selectable signal paths with variable delay times, but when delay cells are enabled or disabled, signal inconsistencies and glitches occur because the NAND gates do not store signal information
Solution Approach 1:
The patent introduces tri-state inverters as intermediary elements between the control logic and the delay path. These inverters act as mediators that conditionally connect or disconnect delay cells from the signal path based on control signals, thereby enabling reconfiguration without causing signal glitches. The tri-state inverters buffer the control action and ensure clean transitions in the signal path.
Solution Approach 2:
The control logic determines the desired delay configuration in advance and activates the appropriate tri-state inverters before the signal needs to pass through the reconfigured path. This preliminary setup ensures that when the signal propagates, the path is already stable and glitch-free.
2Duration of action of moving object
If the number of delay cells is increased to extend delay time, then the maximum delay capability is improved, but the device complexity and signal path length increase
Solution Approach 1:
The patent implements a dynamic control mechanism where tri-state inverters are selectively enabled or disabled based on the desired delay time. This allows the delay line to adapt its effective length dynamically rather than requiring all possible delay cells to be permanently present in the circuit, reducing static complexity while maintaining maximum delay capability when needed.
Solution Approach 2:
The delay line is divided into multiple segments or stages, each controlled by independent tri-state inverters. This segmentation allows the system to achieve long delay times by cascading multiple controllable segments rather than using a single long fixed delay path, thereby managing complexity through modular organization.
3Reliability
If tri-state inverters are used to conditionally connect delay cells, then signal glitches are prevented during reconfiguration, but the device complexity increases due to additional control circuitry
Solution Approach 1:
The control functions of multiple tri-state inverters are merged into a unified control logic unit that generates appropriate control signals for each inverter based on the desired delay configuration. This consolidation reduces the overall control circuitry complexity compared to having independent control logic for each inverter, while still maintaining glitch-free operation.
Data Source
AI summary
Some embodiments provide real-time variable delays in a delay line. In some of these embodiments, the real-time variable delays may be enable without producing clock glitches. In an embodiment, delay cells in a delay line may be coupled together in a chain to form a lattice of inverters providing different paths of signal propagation. Each path may have a different number of inverters; each inverter adding a known processing time associated with the signal inversion process. In some embodiments, an input signal may be propagated in an inverted or non-inverted form to the inputs of multiple inverters in the lattice, including the inputs of inverters through which the input signal does not propagate. A desired delay time may be obtained in an embodiment by selecting a path containing a desired number and configuration of inverters. The path may be selected in an embodiment using switchably enabled inverters.