Configurable Delay Element With Glitch-Less Low-Power Phase Shifting
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Solution Overview
Problem
Existing delay elements in receiver interfaces face issues with power consumption and glitches due to the need for all buffers to toggle when applying a phase shift, leading to data corruption and word misalignment during delay code updates.
Innovation Solution
The proposed configurable delay element uses multiple delay chains and muxes to selectively enable and disable buffer stages based on a 7-bit delay code, reducing power consumption by powering down unused stages and employing a controller to update the delay code during stable buffer states, preventing glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all buffers in the delay chain are enabled to provide phase shift, then the phase shift function is achieved, but power consumption increases and glitches occur during delay code updates
Solution Approach 1:
The delay chain is segmented into multiple independent buffer stages that can be selectively enabled or disabled. Instead of having all 128 buffers continuously active, the system divides them into groups controlled by different enable signals, allowing only the necessary portion to remain active at any given time, thereby reducing power consumption while maintaining the required phase shift function.
Solution Approach 2:
The buffer enable states are dynamically adjusted based on the delay code value. When a delay code update occurs, the system transitions buffers from enabled to disabled states in a controlled sequence, ensuring that the output remains stable throughout the transition. This dynamic control prevents glitches while optimizing power consumption by keeping only necessary buffers active.
2Measurement precision
If delay code is updated dynamically to track V/T variations, then the delay accuracy is maintained, but glitches occur causing data corruption
Solution Approach 1:
Before updating the delay code to track voltage and temperature variations, the system prepares the buffer enable states in advance. The new delay code is validated and the corresponding buffer transitions are planned, ensuring that the output signal remains stable throughout the update process. This preliminary preparation prevents glitches that would otherwise cause data corruption.
Solution Approach 2:
The system monitors the output signal stability during delay code updates and uses feedback control to ensure smooth transitions. When V/T variations require delay adjustment, the feedback mechanism ensures that buffer enable transitions are synchronized with the clock signal phases, preventing output glitches while maintaining accurate delay tracking.
3Reliability
If multiple buffers are kept active to reduce glitches, then data integrity is improved, but power consumption increases
Solution Approach 1:
Different portions of the delay chain are assigned different enable states based on their specific function and the current delay requirement. Instead of uniformly keeping all buffers active, the system applies local quality control where only the buffers necessary for the current delay setting remain enabled, while others are disabled to reduce power loss without compromising data integrity.
Data Source
AI summary
In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.