Phase Interpolation Circuit for Linear Clock Phase at High Bit Rates
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Solution Overview
Problem
Existing phase interpolation circuits in CDR circuits face challenges in achieving linear phase change of the clock signal with respect to the PI code, particularly at high bit rates, due to non-linear phase shift and increased complexity with more reference clock phases.
Innovation Solution
A phase interpolation circuit comprising multiple mixers and a PI code generating circuit that weights and combines reference clock signals with specific phase differences, using a reduced number of phases and adjusted current ratios to generate clock signals with improved linearity, while maintaining a simpler circuit configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a phase interpolation circuit uses more reference clock phases to achieve better phase interpolation performance, then the phase linearity improves, but the circuit complexity increases
Solution Approach 1:
The phase interpolation range is segmented into multiple bands, with each band handled by a dedicated interpolation circuit. Each circuit uses only 4 reference clock phases to cover a specific phase range, avoiding the need for a large number of phases across the entire interpolation range while maintaining good phase linearity within each band.
Solution Approach 2:
Different interpolation circuits are designed with optimized weighting coefficients tailored to their specific phase bands. This local optimization ensures that each circuit achieves the best possible phase linearity for its designated range, rather than using a uniform approach across all phases.
2Device complexity
If the phase interpolation circuit is simplified to reduce complexity, then the circuit size decreases, but the phase linearity deteriorates
Solution Approach 1:
By dividing the interpolation range into multiple bands and using simple 4-phase interpolation circuits for each band, the overall circuit complexity is reduced while maintaining good phase linearity through the segmented approach. Each simple circuit is optimized for its specific band, compensating for the simplicity through strategic division of the phase range.
3Productivity
If the phase interpolation circuit operates at high bit rates, then the data reception speed improves, but the phase difference detection accuracy decreases due to non-linear phase shift
Solution Approach 1:
Segmenting the phase interpolation into multiple bands with dedicated circuits allows for more accurate phase difference detection within each band, even at high bit rates. The segmentation reduces the non-linear phase shift effects within each individual band, improving detection accuracy while maintaining high data reception speed.
Solution Approach 2:
The weighting coefficients in each interpolation circuit are optimized for their specific phase bands and operating conditions. By adjusting these parameters according to the phase band and operating frequency, the circuit maintains accurate phase difference detection across high bit rates while accommodating the non-linear phase shift characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves improved linearity of the clock signal phase with respect to the PI code, comparable to more complex configurations, while reducing circuit complexity and size, and is applicable across a range of frequencies.
Implementation Method 1
a first mixer weights a plurality of reference clock signals having mutually different phases with a first ratio, combines the weighted reference clock signals, and generates first intermediate signals; a second mixer weights the plurality of reference clock signals having mutually different phases with a second ratio equal to the first ratio, combines the weighted reference clock signals, and generates second intermediate signals
Implementation Method 2
an output signal is generated by combining the first intermediate signals and the second intermediate signals
Data Source
AI summary
A phase interpolation circuit includes: a first circuit configured to generate a first intermediate signal by weighting first reference signals having different phases with a first ratio and combining weighed first reference signals; a second circuit configured to generate a second intermediate signal by weighing second reference signals having phases different from the phases of the first reference signals by a certain value with a second ratio equal to the first ratio and combining weighted second reference signals; and a third circuit configured to generate an output signal by combining the first intermediate signal and the second intermediate signal.