Clock Frequency Doubler for Serial Flash Memory Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high cost and inefficiency of testing semiconductor memory devices, particularly serial flash memories, due to the need for high-speed testing that often cannot be achieved with conventional memory testers operating at frequencies lower than the devices' operating speeds, leading to inadequate testing and potential failure in final products.
Innovation Solution
A method and apparatus for memory device testing that generates a higher clock frequency than the tester, using techniques such as EXCLUSIVE-OR circuits or PLLs to produce a second clock signal at twice the initial frequency, enabling high-speed wafer-level testing of serial flash memory devices and other non-volatile memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional memory testers are used to test serial flash memory devices, then the testing process is simpler and equipment cost is lower, but the clock frequency provided by the tester is insufficient to achieve high-speed testing required by modern memory devices
Solution Approach 1:
The patent introduces an intermediary clock frequency doubling circuit between the conventional memory tester and the serial flash memory device under test. This circuit receives the base clock signal from the tester and generates a doubled-frequency clock signal, enabling high-speed testing without requiring an expensive high-frequency tester. The intermediary circuit effectively bridges the gap between the tester's limited clock capability and the device's high-speed requirements.
Solution Approach 2:
The patent changes the clock frequency parameter by implementing a frequency doubling mechanism. The clock frequency doubling circuit transforms the base clock frequency (e.g., 50 MHz) into a doubled frequency (e.g., 100 MHz), allowing the testing system to operate at the required high speed while using conventional testing equipment. This parameter transformation resolves the contradiction between equipment capability and testing speed requirements.
2Reliability
If high-speed testing is implemented to match memory device operating speeds, then testing accuracy and reliability improve, but equipment cost increases significantly
Solution Approach 1:
The clock frequency doubling circuit serves as a cost-effective intermediary solution that enables reliable high-speed testing without investing in expensive high-frequency testing equipment. By doubling the clock frequency through a simple circuit implementation, the system achieves the necessary testing speed and reliability while keeping equipment costs comparable to conventional testing setups.
Solution Approach 2:
The patent employs a simple, low-cost clock frequency doubling circuit implementation that can be easily manufactured and integrated. Rather than purchasing expensive high-frequency testers, the invention uses an affordable frequency multiplication approach that achieves the same testing reliability at a fraction of the equipment cost.
3Productivity
If conventional testing equipment is used, then equipment cost is lower, but testing speed is insufficient leading to inadequate testing of memory devices at their operating frequency
Solution Approach 1:
The patent transforms the clock frequency parameter from the base frequency provided by conventional testers to a doubled frequency that matches the memory device's operating speed. This parameter change ensures that testing occurs at the appropriate speed to properly evaluate high-speed memory devices, thereby improving both testing productivity and measurement adequacy simultaneously.
Solution Approach 2:
The clock frequency doubling circuit acts as an intermediary that enhances the output capability of conventional testers. It takes the limited-frequency clock signal from inexpensive equipment and converts it to a high-frequency signal suitable for adequate testing of fast memory devices, thus resolving the contradiction between equipment cost and testing adequacy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient high-speed testing of memory devices at higher frequencies, reducing testing costs and ensuring thorough evaluation of memory devices without requiring expensive high-frequency testers, while being compatible with conventional design and process technologies.
Implementation Method 1
coupling the first and third clock signals to an EXCLUSIVE-OR circuit, which configured for generating the second clock signal. The second clock signal thus generated is characterized by a clock frequency that is twice the first clock frequency
Implementation Method 2
coupling the first clock signal to a phase-locked loop circuit which produces the second clock signal having a frequency that is twice the frequency of the first clock signal
Data Source
AI summary
Method and apparatus for memory device testing at a higher clock rate than the clock rate provided by a memory tester. The method includes providing a memory tester capable of generating a first clock signal characterized by a first clock frequency, and applying the first clock signal to the memory device. The method also includes receiving a command for activating a high-clock-frequency test mode. The method generates a second clock signal in the memory device in response to the first clock signal. The second clock signal is characterized by a second clock frequency which is higher than the first clock frequency. The method then tests the memory device at the second clock frequency. In a specific embodiment, the method is applied to a serial flash memory device. The invention can also be applied to testing and operating other memory devices or systems that include synchronized circuits.