Clock Circuit Frequency Testing With Elevated Input Thresholds
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Solution Overview
Problem
Current integrated circuit testers require excessive time to determine whether the frequency of a feedback clock signal is locked to the input clock signal and to determine if the output clock signal is above a threshold frequency, as they rely on precise counter synchronization and narrow tolerances, which increase test duration.
Innovation Solution
The system sets the input clock signal to an elevated frequency with a higher tolerance, allowing counters to determine if the feedback clock signal's frequency is above an input threshold frequency, thereby reducing test time by shortening the test interval and requiring fewer counter bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the test interval is increased to decrease frequency tolerance and improve measurement precision, then the frequency locking determination becomes more accurate, but the test time increases significantly
Solution Approach 1:
The patent changes the test frequency parameter to an elevated frequency (higher than the nominal operating frequency). This allows the use of a wider frequency tolerance range at the elevated frequency while still accurately determining if the output frequency exceeds the threshold at the nominal frequency, thereby reducing the required test interval duration
Solution Approach 2:
The patent performs a preliminary frequency check by measuring whether the feedback clock frequency exceeds a threshold at an elevated test frequency. This preliminary action provides sufficient information to determine frequency locking without requiring the lengthy precise measurement that would be needed at the nominal frequency, thus reducing overall test time
2Measurement precision
If the frequency tolerance is decreased to improve measurement precision, then the frequency locking determination becomes more accurate, but the number of counter bits required increases
Solution Approach 1:
By measuring at an elevated frequency with a wider tolerance range, the patent reduces the precision requirements of the counter. This allows the use of fewer counter bits while still achieving sufficient accuracy for determining whether the output frequency exceeds the threshold, thereby reducing device complexity
3Reliability
If the test interval is increased to accurately determine frequency locking, then the frequency measurement becomes more reliable, but productivity decreases due to longer test duration
Solution Approach 1:
The patent changes the measurement approach by using an elevated test frequency with a wider tolerance range. This allows for a shorter test interval that maintains sufficient reliability for determining frequency locking, thereby improving testing productivity without sacrificing essential measurement reliability
Data Source
AI summary
A test circuit determines whether a frequency of an output clock signal of a clock circuit is above an output threshold frequency. An input clock signal of the clock circuit is set to an elevated frequency that is higher than a specified frequency. A first counter counts the number of clock cycles of the input clock signal in a test interval to within a tolerance of the elevated frequency. The tolerance of the elevated frequency is higher than a tolerance of the specified frequency. A second counter counts the number of clock cycles of a feedback clock signal in the test interval. A comparator determines whether the frequency of the output clock signal is above the output threshold frequency based on the number of clock cycles of the input clock signal and the number of clock cycles of the feedback clock signal.