Clock Gate Control for At-Speed IC Testing Across Clock Domains
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Solution Overview
Problem
Conventional integrated circuits (ICs) face challenges in at-speed testing due to complex clock management and the need for additional test registers and chopping circuits, which increase size and design complexity, and impose timing overhead.
Innovation Solution
The proposed solution involves a clocking system with clock gate controllers and clock gates that generate at-speed clock signals with launch and capture pulses directly from a reference clock signal, eliminating the need for further division and chopping circuits, and allowing data launch and capture operations to be executed in the same or different clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock management with dividers and chopping circuits is used to generate launch and capture pulses, then the testing functionality is achieved, but the device complexity and size increase due to additional test registers and chopping circuits
Solution Approach 1:
The patent extracts the pulse generation functionality from the conventional complex clock management system by using a simple counter circuit that counts reference clock cycles to generate launch and capture pulses. This removes the need for dedicated test registers and chopping circuits, significantly reducing device complexity while maintaining testing functionality.
Solution Approach 2:
The counter circuit serves multiple functions: it counts reference clock cycles, generates launch pulses at predetermined frequencies, generates capture pulses with configurable delays, and enables both intra-domain and inter-domain testing. This multi-functionality eliminates the need for separate dedicated circuits for each function.
2Reliability
If additional test registers and chopping circuits are added to enable at-speed testing, then the testing capability is improved, but the area and size of the IC increase
Solution Approach 1:
The patent removes the area-consuming test registers and chopping circuits by implementing pulse generation through a compact counter circuit that uses existing reference clock signals. The counter-based approach generates the necessary launch and capture pulses without requiring additional large-scale test infrastructure.
Solution Approach 2:
The patent changes the approach from hardware-intensive pulse generation to a parameter-based solution where pulse timing and frequency are controlled by programmable counter values. This allows flexible testing configurations without adding physical circuit area.
3Reliability
If complex clock management circuits are used for generating launch and capture pulses, then the testing functionality is achieved, but timing overhead increases
Solution Approach 1:
The patent eliminates timing overhead introduced by complex clock management by directly using the reference clock signal and a simple counter to generate launch and capture pulses. This direct approach removes multiple clock division and synchronization stages that would otherwise introduce timing delays.
Solution Approach 2:
The counter circuit is pre-configured with predetermined values that define the timing relationships between launch and capture pulses. This preliminary setup allows the system to generate accurately timed pulses without requiring complex real-time calculation or adjustment, reducing timing overhead.
Data Source
AI summary
An integrated circuit (IC), including a clocking system, a plurality of clock gate controllers, and a plurality of clock gates, is provided. During a capture phase of an at-speed testing of the IC, the clocking system generates an at-speed clock signal including launch and capture pulses that are extracted from a reference clock signal based on a capture phase frequency. The plurality of clock gate controllers generates a plurality of enable signals such that for the launch pulse, one enable signal is asserted, and for the capture pulse, the same or different enable signal is asserted. Each of the plurality of clock gates is activated based on an assertion of a corresponding enable signal. Further, during the capture phase, one or more activated clock gates enable the at-speed testing of the IC based on the at-speed clock signal.