Clock-Gated Impedance Measurement for On-Chip Power Networks

The patent extracts the impedance measurement function from the traditional current sink approach and implements it using a voltage signal injection method with a voltage source. The measurement is performed by injecting a voltage signal through the power delivery network and measuring the resulting current, rather than using a current sink to directly measure impedance. This extraction allows the system to achieve impedance measurement capability while avoiding the large area occupation and leakage current problems of current sinks.

The patent converts the harmful effect of using active measurement components into a benefit by using a voltage source that naturally drives current through the impedance without generating leakage current. The measurement methodology is transformed to use voltage injection where the current is a result of the voltage signal passing through the network impedance, rather than being forced by a current sink. This conversion eliminates the leakage current problem while maintaining measurement capability.

The patent implements a feedback mechanism where the phase alignment between the enable signal and clock signal is continuously monitored and adjusted. The feedback loop detects phase differences and modifies the enable signal timing to achieve edge alignment, ensuring that the gated clock signal is not affected by jitter. This feedback approach maintains signal stability and reliability while providing a systematic method to handle the alignment requirement.