Clock-Gated Shift Register for Low-Transition Power Saving
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Solution Overview
Problem
Digital shift registers consume significant power due to clocking activity even when flip-flop stages do not change state, leading to wastage of power in applications like image processing where most flip-flops remain inactive during scanning.
Innovation Solution
Incorporating a clock gating block in each stage of the shift register to prevent digital activity in non-changing stages and using a resistively-loaded clock buffer to reduce power dissipation by only propagating the clock signal to stages that will change state, thereby minimizing capacitance on the global clock bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a typical digital shift register uses a global clock signal to clock all flip-flops, then the shift register can maintain simple structure and uniform operation, but it consumes significant power due to clocking activity in all stages even when data does not change
Solution Approach 1:
The patent segments the global clock signal distribution by introducing individual clock gating blocks for each flip-flop stage. Each clock gating block independently controls the clock signal to its associated flip-flop based on whether data change is detected, thereby segmenting the power consumption at the stage level rather than having uniform clocking across all stages.
Solution Approach 2:
The patent applies local quality by making each clock gating block have the specific function of detecting data changes locally at its associated flip-flop stage. The clock gating block examines the current and next state of its local flip-flop and only enables clocking when a state transition is detected, creating localized intelligent power management rather than global uniform clocking.
2Loss of energy
If clock gating blocks are added to each stage to prevent digital activity in non-changing stages, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The clock gating block is designed as a universal multi-functional unit that combines data change detection, clock signal gating, and state transition monitoring into a single integrated block. This universal block can be replicated at each stage, providing multiple functions (detection, gating, control) without requiring separate dedicated circuits for each function.
Solution Approach 2:
The clock gating block acts as an intermediary component between the global clock signal source and the individual flip-flops. It mediates the clock signal distribution by conditionally passing or blocking the clock based on detected data changes, thereby introducing intelligent control without directly modifying the flip-flop internal structure.
3Loss of energy
If a resistively-loaded clock buffer is used to propagate clock signals only to changing stages, then capacitance on the global clock bus is minimized and power is reduced, but the buffer design becomes more complex
Solution Approach 1:
The patent changes the electrical parameters of the clock buffer by using resistive loading instead of traditional capacitive or inductive loading. The resistively-loaded clock buffer modifies the output impedance and signal propagation characteristics, enabling it to drive clock signals selectively to only those stages that require clocking, thereby reducing the total capacitive load on the global clock bus.
Data Source
AI summary
A gated-clock shift register including a series of clocked flip-flops with preceding outputs connected to subsequent inputs as a horizontal digital shift register. Each flip-flop (or other state holding device) includes a clock buffer between the respective flip-flop's clock, and the global clock. Each clock buffer propagates the clock signal when it determines the associated flip-flop will have a state change during that clock cycle (e.g., via an XOR of the flip-flops input and output signals). In the absence of a state change, that buffer does not propagate the clock signal, essentially only clocking the relevant flip-flops. Further, the clock buffer may be implemented with only NMOS devices (or alternatively, only PMOS devices), which offers power savings over an otherwise required CMOS implementation.