Clock Gating Device for Independent Core Testing

The patent divides the clock distribution system into multiple independent clock domains, each serving a specific core. Each clock domain includes its own clock gating device that can independently generate shift and capture clock pulses. This segmentation allows each core to be tested independently while sharing the same physical clock mesh infrastructure, resolving the contradiction between versatility and complexity.

The patent introduces clock gating devices as intermediary components between the system clock signal source and the individual cores. These gating devices act as mediators that can selectively enable or disable clock signals to specific cores and generate the required shift/capture pulse sequences. This intermediary layer provides the needed independence without requiring fundamental changes to the clock mesh architecture.

The patent employs periodic clock gating where clock signals are delivered in pulsed sequences rather than continuously. The clock gating devices generate periodic enable signals that activate the clock signal only during required operation windows. This periodic action maintains high-speed operation when needed while significantly reducing average power dissipation during idle or testing periods.

The patent implements dynamic clock frequency and enable control through clock gating devices that can adjust clock delivery based on operational requirements. During normal operation, full-frequency clocks are provided to maximize speed. During testing or idle periods, the clock gating dynamically reduces or suspends clock signals to minimize power consumption, thus adapting the system's energy consumption to its instantaneous needs.