Clock Gating Circuit Topology for Lower Dynamic Clock Power
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Solution Overview
Problem
In semiconductor integrated circuits, clock trees face issues with timing errors due to differences in clock signal arrival times and increased power consumption as ICs become smaller and more complex, affecting performance and area efficiency.
Innovation Solution
A clock gating circuit is implemented using a NOR logic gate, transmission gate, and cross-coupled transistors, reducing the number of transistors toggled by the inverted clock signal, thereby minimizing dynamic clock power consumption and occupying less area compared to traditional clock gating cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If traditional clock gating cells are used, then clock signal distribution is achieved, but the number of transistors toggled by inverted clock signal increases dynamic power consumption
Solution Approach 1:
The patent extracts and eliminates the inverter component from the traditional clock gating cell architecture. By removing the inverter that generates the inverted clock signal, the design reduces the number of toggling transistors and associated dynamic power consumption while maintaining the essential clock gating functionality through alternative circuit configurations.
Solution Approach 2:
The patent changes the operational parameters of the clock gating circuit by modifying the transistor switching behavior. Instead of using an inverted clock signal to control transistor switching, the design employs direct clock signal control with modified enable logic, thereby reducing unnecessary transistor transitions and dynamic power consumption.
2Reliability
If more transistors are used in clock gating cells, then clock signal control is improved, but area usage increases
Solution Approach 1:
The patent removes redundant transistors and the inverter component from the clock gating cell, reducing the overall circuit area. The essential clock signal control functionality is maintained through optimized transistor arrangements that eliminate unnecessary components while preserving control accuracy.
Solution Approach 2:
The patent merges the clock signal control function with the enable logic function into a more integrated circuit structure. By combining these functions and eliminating separate inverter stages, the design achieves reliable clock control with reduced transistor count and smaller area footprint.
3Productivity
If clock signal arrives at different circuits at different times, then distribution is achieved, but timing errors occur
Solution Approach 1:
The patent applies local optimization to the clock gating circuit by ensuring that the reduced transistor configuration maintains consistent switching characteristics across different circuit instances. This local quality control helps minimize variations in clock signal arrival times at different circuits while preserving wide distribution coverage.
Data Source
AI summary
A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor of a first type and a first pull-up transistor of the first type. The input circuit is configured to set a first control signal of a first node in response to a first or second enable signal. The cross-coupled pair of transistors is coupled between the first node and an output node. The first transistor is coupled between the first and a second node. The first pull-up transistor includes a first gate terminal, a first drain terminal and a first source terminal. The first gate terminal is configured to receive an inverted clock input signal. The first drain terminal is coupled to the second node and the first transistor. The first pull-up transistor is configured to adjust a clock output signal responsive to the inverted clock input signal.