Clock Gating Circuit With Single-Delay Setup and Glitch Control
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Solution Overview
Problem
Modern semiconductor chips face challenges in reducing power consumption due to the high switching frequency of internal nodes in circuits like flip-flop and latch circuits, making it difficult to balance performance and power usage effectively, particularly in meeting setup and hold times for clock gating techniques.
Innovation Solution
The implementation of a clock gating circuit with a setup time provided by a propagation delay through a single transistor, using serially connected nmos transistors and a delayed and inverted clock signal to manage power by disabling clock signals efficiently, along with a pulse domino NAND gate and delay element for latch hold times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conditional techniques are used to disable clock signals for power reduction, then power consumption is reduced, but meeting setup and hold times becomes difficult as clock frequencies increase
Solution Approach 1:
The enable signal is latched in advance using a pulse domino NAND gate that captures the enable condition before the critical clock edge. This preliminary action ensures the enable state is established and held stable prior to the clock transition, allowing the clock gating to occur without violating setup or hold time requirements at high frequencies
Solution Approach 2:
A delay element is introduced as an intermediary between the enable signal path and the clock gating control. This delay element provides the necessary hold time by delaying the propagation of the enable signal, ensuring that the clock gating control signal remains stable throughout the entire clock cycle and preventing glitches while maintaining power reduction
2Productivity
If clock frequency is increased to improve performance, then productivity increases, but meeting setup and hold times for clock gating becomes more difficult
Solution Approach 1:
The enable condition is captured and latched in advance using the pulse domino NAND gate structure, which evaluates and stores the enable state before the critical clock edge arrives. This preliminary action decouples the enable signal timing from the high-frequency clock transitions, allowing the system to operate at higher frequencies without compromising setup and hold time compliance
Solution Approach 2:
A delay element is strategically placed in the signal path to provide the necessary hold time margin. This intermediary component ensures that the clock gating control signal remains stable throughout the entire clock cycle, creating a buffer that allows high-frequency operation while maintaining reliable timing margins
Data Source
AI summary
A system and method for providing efficient clock gating capability for functional units are described. A functional unit uses a clock gating circuit for power management. A setup time of a single device propagation delay is provided for a received enable signal. When each of a clock signal, the enable signal and a delayed clock signal is asserted, an evaluate node of the clock gating circuit is discharged. When each of the clock signal and a second clock signal is asserted and the enable signal is negated, the evaluate node is left floating for a duration equal to the hold time. Afterward, the devices in a delayed onset keeper are turned on and the evaluate node has a path to the power supply. When the clock signal is negated, the evaluate node is precharged.