Clock Gating Latch Circuit for Stable Pulse Width Control
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Solution Overview
Problem
The miniaturization of integrated circuits poses challenges in design and manufacturing, particularly in ensuring reliable operation and reducing power consumption, as existing technologies face issues with pulse width variations in clock signals, leading to uncertainties in synchronous logic circuits.
Innovation Solution
The implementation of an enabling latch circuit that generates a latch output signal based on an enable signal and a clock signal, which is used to gate the clock signal, ensuring the latch output signal is latched until the next clock edge, thereby maintaining a consistent duty cycle and reducing the number of transistors driven by the clock logic circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the clock signal is directly gated with the enable signal, then the synchronous logic circuit can be controlled, but pulse width variations occur leading to reliability issues
Solution Approach 1:
An enabling latch circuit is introduced as an intermediary between the enable signal and the clock signal. The latch circuit captures the enable signal at the clock edge and holds it until the next clock edge, eliminating pulse width variations. This mediator ensures that the gated clock signal has consistent width regardless of when the enable signal transitions occur.
Solution Approach 2:
The enable signal is captured and held in the latch circuit before being used to gate the clock signal. By preliminarily storing the enable signal state at the clock edge, the system ensures that the clock gating decision is made based on a stable, synchronized signal rather than a potentially varying pulse width signal.
2Reliability
If more transistors are driven by the clock logic circuit to ensure reliable operation, then reliability improves, but power consumption increases
Solution Approach 1:
The clock logic circuit is relieved of the burden of driving additional transistors for enable signal conditioning. The enabling latch circuit independently processes the enable signal, extracting the clock gating control function from the main clock logic circuit and reducing its transistor driving burden.
Solution Approach 2:
The enabling latch circuit is self-contained, using only two transistors that are already part of the latch structure to generate the gated clock signal. These transistors serve dual purposes: maintaining the latch state and controlling the clock signal, eliminating the need for additional dedicated control transistors.
3Loss of time
If the latch output signal is not latched until the next clock edge, then response time increases, but pulse width variations cause uncertainties
Solution Approach 1:
The latch circuit operates periodically at each clock edge, capturing the enable signal state and holding it until the next clock edge. This periodic operation ensures that the gated clock signal maintains a consistent duty cycle and width, eliminating variations while maintaining deterministic timing behavior.
Solution Approach 2:
The latch circuit provides feedback by holding the enable signal state between clock edges. This feedback mechanism ensures that the clock gating control remains stable and predictable, preventing pulse width variations while maintaining proper synchronization with the clock signal.
Data Source
AI summary
An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, a branch-two transistor, and a clock gating circuit. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is electrically connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is electrically connected to the first node. The clock gating circuit for generating a gated clock signal receives a latch output signal which is latched to a logic level of either a first node signal or a second node signal.