Multi-Threshold Clock Gating Cell for Leakage Power Reduction
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Solution Overview
Problem
Clock gating cells with a single low voltage threshold induce high power consumption due to increased leakage current, which is not effectively managed in existing clock tree designs.
Innovation Solution
A clock gating cell design that operates with multiple voltage thresholds, where the input stage and output stage utilize different voltage thresholds, allowing for reduced leakage current and improved power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a low voltage threshold is used in clock gating cells, then the clock tree performance is improved, but the leakage current increases causing high power consumption
Solution Approach 1:
The patent applies local quality by assigning different voltage thresholds to different stages within the clock gating cell. The input stage uses a first voltage threshold while the output stage uses a second voltage threshold, allowing each stage to be optimized for its specific function rather than using a uniform threshold throughout the entire cell.
Solution Approach 2:
The clock gating cell is segmented into distinct input and output stages, each with independently optimized voltage thresholds. This segmentation allows the input stage to be optimized for signal reception and the output stage to be optimized for signal driving, resolving the contradiction between performance and power consumption.
2Device complexity
If all devices in a clock gating cell operate based on the same voltage threshold, then the design is simple, but power consumption increases due to leakage current
Solution Approach 1:
Different voltage thresholds are assigned to different devices/stages within the clock gating cell based on their specific functional requirements. The input stage devices operate at one threshold while output stage devices operate at another, optimizing power consumption without significantly increasing design complexity.
Data Source
AI summary
A clock gating cell is provided. The clock gating cell includes an input stage and an output stage. The input stage receives a first clock signal and at least one input enable signal and generates a first enable signal corresponding to one of the least one input enable signal according to the first clock signal. The output stage is coupled to the input stage. The output stage receives the first enable signal and the first clock signal and generates a clock gating signal according to the first enable signal and the first clock signal. The input stage operates based on a first voltage threshold, and the output stage operates based on a second voltage threshold. The first voltage threshold is different from the second voltage threshold.