Functional Block Clock Gating for Power and Latency
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Solution Overview
Problem
Existing power-saving techniques for electronic chips, such as deactivating or slowing down a clock signal for large zones, result in prohibitively long latency and disrupt data processing, making them inefficient for reducing on-chip power consumption, especially in mobile devices.
Innovation Solution
Implementing functional block level clock-gating by monitoring the activity level of each block and temporarily disabling or enabling the clock signal for specific inactive clock cycles, using clock gates to manage power consumption without significantly affecting processing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock signal is deactivated or slowed down for large zones of the chip, then power consumption is reduced, but latency increases and data processing is disrupted
Solution Approach 1:
The chip is divided into multiple functional blocks, each with its own activity-level indicator and clock control. Instead of applying clock gating to large zones, the patent segments the chip into smaller functional units that can be independently controlled based on their specific activity levels, allowing fine-grained power management without widespread latency impacts.
Solution Approach 2:
Each functional block receives customized clock control based on its local activity-level indicator. The clock signal is selectively enabled or disabled for specific functional blocks based on their individual power consumption characteristics and activity levels, rather than applying uniform clock control to large zones, thus reducing power where needed while maintaining processing elsewhere.
2Use of energy by moving object
If clock signal is deactivated for large zones, then power consumption is reduced, but data processing performance deteriorates
Solution Approach 1:
The clock control system dynamically adjusts the clock signal to functional blocks based on real-time activity-level indicators. When a functional block becomes inactive, its clock is disabled to save power; when activity is detected, the clock is re-enabled. This dynamic adaptation allows the system to maintain high data processing performance during active periods while reducing power consumption during inactive periods.
Solution Approach 2:
Each functional block essentially manages its own clock control through its activity-level indicator. The functional block's activity state automatically triggers appropriate clock control actions, allowing the system to self-regulate power consumption and performance without external intervention, thereby maintaining overall productivity while reducing power usage.
3Use of energy by moving object
If clock signal is slowed down for the entire chip, then power consumption is reduced, but processing latency increases significantly
Solution Approach 1:
Rather than slowing down the clock for the entire chip, the patent segments the clock control to individual functional blocks. Each block's clock can be independently enabled or disabled based on its activity level, preventing system-wide latency increases while still achieving power savings in inactive blocks.
Solution Approach 2:
The system changes the clock signal parameter (enabled/disabled state) for specific functional blocks based on their activity-level indicators, rather than uniformly slowing down the clock for the entire chip. This selective parameter change allows power reduction without the prohibitive latency penalty of global clock slowing.
Data Source
AI summary
An embodiment of the invention includes receiving an indicator of an activity-level of a functional block within an electronic chip. The functional block is configured to receive a clock signal from a clock signal generator. The clock signal to at least a portion of a functional block is disabled for a number of inactive clock cycles during a clock segment of the clock signal. The clock segment has a specified number of clock cycles and the number of inactive clock cycles is defined based on the activity-level and the specified number of clock cycles of the clock segment.