Energy Efficient ICT TRIZ Cases

Time-multiplexing one analog-to-digital converter between signal paths eliminates gain and phase differences that degrade receiver image rejection.

Processor cores store evicted victim lines in neighboring core caches to reduce latency.

Clock gates disable inactive cycles in functional blocks to reduce chip power consumption without increasing processing latency.

Elastic computing framework segments workloads and dynamically selects optimal implementations on GPUs or FPGAs to resolve power-performance tradeoffs.

A power supply system prioritizes self-generation and stored energy over commercial sources to reduce reliance on grid electricity.

Embedded firmware in the Alert Sending Device manages timers and packet processing to provide robust remote management without requiring an operating system.

An inter-partition bridge manages sequestered devices via mock interfaces, preventing high power usage from unmonitored resources.

Dynamic power control adjusts processor clock frequency and supply voltage based on real-time workload assessment.

Application server queries home subscriber server for terminal information to select the correct network domain.

Looping back arbitration information allows direct interconnect access, reducing latency and power consumption caused by duplicate data maintenance.

A voltage identifier sorting system selects optimal processor voltages using measured current characteristics to minimize energy consumption.

A portable terminal maps cellular and WLAN data to enable efficient network discovery.

Centralizing security and communication management on an off-load processor reduces device complexity while maintaining robust encryption capabilities.

A node uses a directional antenna to forward packets via relative-location information.

An optical touchpad uses a sensing array to detect object distance and selectively deactivate the motion detector to conserve energy.

A wireless sensor network distributes data packets across multiple paths to minimize power consumption and transmission time.

A modular integrated circuit uses a hub module to manage spoke modules via common interfaces.

A normalized power utilization index calculates energy consumption per unit of workload to predict future server power usage.

A link group management unit dynamically switches physical links between active and power save modes based on measured traffic levels.

A perturbed thermal model estimates target location temperatures using internal sensor data without direct ambient measurement.

Non-magnetic circuitry replaces bulky transformers in Ethernet networks, eliminating electromagnetic interference and PCB space constraints.

Correlates monitored network events with power profiles to estimate energy usage without hardware installation.

A programmable baseband digital signal processor uses a reconfigurable interconnect network to link memory and accelerator units for flexible data routing.

A power control apparatus manages core activity using memory and thread information alongside CPU usage data.

Stacked-die memory architecture segments storage into independent vaults to resolve bandwidth limits and power consumption trade-offs.

A common deep doping well reduces digital noise and leakage currents while enabling efficient sleep mode power management for mobile communication devices.

Continuous line monitoring enables dynamic rate adjustments without re-initialization, resolving service continuity conflicts during provisioning changes.

A network aggregation device configures diverse physical links into a single logical connection to increase combined transfer rates.

A semiconductor device monitors received data to detect specific frames for mode switching without wakeup signals.

A server calculates a delay period based on client latency to throttle secondary requests and prevent resource monopolization.

A memory link power management system transitions components into low power states based on detected operating conditions.

A memory controller detects inactivity and commands a buffer to enter a reduced power state.

Transitioning the memory subsystem from full power to low power states reduces consumption while maintaining system performance.

Hardware power control logic monitors domain ID signals to transition unused slave devices into low-power states.

A client module displays a device status icon to instruct the electronic device to exit energy-saving mode.

A data processing apparatus manages multiple power modes through dynamic transition logic that selects between standby and high-speed startup states.

Adaptive throttling adjusts throttle multipliers to maintain an ideal request rate.

Automated probe message exchange verifies remote identifiers to assign ports, reducing configuration complexity while maintaining network redundancy.

The GPU context controller translates neutral display lists to switch between dissimilar GPUs, eliminating user intervention and reducing power consumption.

A SATA interface selects power saving modes independently of transmitter requests to balance energy use and wake-up response.

A network apparatus transmits start completion notices to a terminal via a router for remote monitoring.

A memory device dynamically switches between data masking and data bus inversion functionalities using a single shared input pin.

A network switch establishes Layer 2 reservations for ingress queue capacity to preserve data frames from source stations during transmission.

Synchronizing event ring updates with CPU interrupts reduces power consumption by minimizing frequent mode transitions in USB host controllers.

A terminal control device monitors CPU and GPU voltage and frequency to adjust hardware operation modes.

Off-chip voltage source reduces supply voltages within a network adapter chip, eliminating current draw while preventing reliability stress on I/O cells.

A graphics memory management system shares idle GPU memory with general applications via dynamic allocation and access translation.