Memory Loopback Control for Shared Access Latency
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Solution Overview
Problem
Existing memory sharing techniques between processing devices in systems with multiple processors are inefficient, leading to high processing load, reduced memory availability, long latency, and increased power consumption due to duplicate data maintenance and private bus usage.
Innovation Solution
A memory system where controller devices access memory arrays through interconnects, with loopback mechanisms for control and address information, and arbitration information routing via memory devices to enable efficient access and dynamic allocation of memory resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If processors cooperate to maintain duplicate images of data in different memory devices, then memory sharing is enabled, but processing load increases and memory availability decreases
Solution Approach 1:
The patent merges multiple memory devices into a unified shared memory space accessible by multiple processors. Instead of maintaining separate duplicate data images in each processor's dedicated memory, the system allows processors to access a common memory pool through an interconnect fabric, eliminating redundant data storage and reducing processing overhead for maintaining data consistency across multiple memory copies.
Solution Approach 2:
The memory system implements universal access where any processor can access any memory device through the interconnect fabric. The memory devices are designed with multiple interfaces that allow them to serve multiple processors simultaneously, enabling a single memory device to function as both dedicated and shared memory depending on access patterns and arbitration outcomes.
2Adaptability or versatility
If a private bus is provided between processors for memory access, then memory sharing is enabled, but latency increases and bandwidth decreases
Solution Approach 1:
The system segments the memory access path by providing direct point-to-point interconnects between processors and memory devices, eliminating the need for a single shared private bus. This segmentation allows multiple simultaneous access paths to exist, enabling parallel memory operations and reducing contention-induced latency.
Solution Approach 2:
The patent introduces an interconnect fabric as an intelligent intermediary between processors and memory devices. This fabric includes arbitration logic and routing capabilities that dynamically manage access requests, allowing multiple processors to access multiple memory devices concurrently with minimized latency through efficient request routing and arbitration.
3Adaptability or versatility
If data is forwarded between devices in multiple stages, then memory sharing is enabled, but power consumption increases
Solution Approach 1:
The system performs preliminary action by pre-establishing direct interconnect paths between processors and memory devices during system initialization or configuration. This allows data to be accessed directly through optimized paths without requiring multiple staging operations, reducing the number of active components and thereby lowering power consumption during memory access operations.
Data Source
AI summary
A memory device loops back control information from one interface to another interface to facilitate sharing of the memory device by multiple devices. In some aspects, a memory controller sends control and address information to one interface of a memory device when accessing the memory device. The memory device may then loop back this control and address information to another interface that is used by another memory controller to access the memory device. The other memory controller may then use this information to determine how to access the memory device. In some aspects a memory device loops back arbitration information from one interface to another interface thereby enabling controller devices that are coupled to the memory device to control (e.g., schedule) accesses of the memory device.