Ping-Pong ADC Architecture for I-Q Mismatch Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In wireless communication systems, the mismatch between in-phase (I) and quadrature (Q) components due to gain and phase differences in parallel signal paths leads to sub-optimal receiver performance, particularly in systems like image-reject and homodyne receivers, where incomplete cancellation of image frequencies degrades signal-to-noise ratio (SNR).
Innovation Solution
Sharing a single pipelined analog-to-digital converter (ADC) between the I and Q components, known as 'ping-ponging,' ensures both components are processed by the same circuitry, reducing I-Q mismatch and eliminating many dominant sources of mismatch, thereby improving system performance and reducing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate ADCs are used to process I and Q components in parallel signal paths, then each component can be processed simultaneously, but I-Q mismatch occurs due to gain and phase differences between the parallel paths
Solution Approach 1:
The patent merges the processing of I and Q components by using a single shared ADC instead of separate ADCs. The ADC is time-multiplexed to sequentially convert I and Q samples, ensuring both components undergo identical conversion processes with the same gain and phase characteristics, thereby eliminating I-Q mismatch while maintaining processing capability.
Solution Approach 2:
The patent implements periodic switching between I and Q component processing using a single ADC. The ADC alternates between converting I samples and Q samples in a periodic manner, controlled by a switch that toggles based on timing signals, achieving time-interleaved processing that eliminates mismatch between parallel paths.
2Measurement precision
If a single ADC is shared between I and Q components, then I-Q mismatch is reduced, but the ADC must operate at higher speed to handle both components
Solution Approach 1:
The ADC operates in periodic cycles, alternating between I and Q component conversion. By dividing the processing into sequential periods rather than requiring simultaneous parallel operation, the ADC can process both components at its native speed without needing to operate at double the speed that would be required for true simultaneous conversion of both paths.
Solution Approach 2:
The system dynamically switches the ADC's input source between I and Q components based on timing requirements. This dynamic time-multiplexing approach allows the ADC to operate at a manageable speed while still handling both signal paths, as the switching occurs at the sample rate rather than requiring the ADC to process both paths simultaneously at higher speeds.
3Productivity
If separate ADCs are used for I and Q components, then processing can be simultaneous, but system complexity and cost increase
Solution Approach 1:
The patent combines what would traditionally require two separate ADCs into a single shared ADC resource. By time-multiplexing the single ADC between I and Q components, the system maintains the functional capability to process both components while reducing the hardware count, complexity, and associated costs of having two independent ADC circuits.
Solution Approach 2:
The single ADC is designed to serve multiple functions by sequentially processing both I and Q components. This multi-functional approach allows one ADC to replace what would traditionally require two dedicated ADCs, reducing system complexity while maintaining the ability to process both signal paths effectively through time-interleaved operation.
Data Source
AI summary
The invention provides a receiver for use in a wireless communication system that substantially reduces mismatch between an in-phase (I) component and a quadrature (Q) component of a received signal. The receiver achieves this by sharing or “ping-ponging” an analog-to-digital converter (ADC) between the I and Q components. By sharing a single pipelined ADC between the I and Q components, both the I and Q components are processed by the same circuitry inside the pipelined ADC thereby eliminating many dominant sources of I-Q mismatch. The pipelined ADC operates at approximately twice the speed as other circuit components. Consequently, I-Q mismatch, which negatively affects performance, may be substantially reduced. At the same time, system complexity, cost, and power dissipation are reduced by eliminating an additional ADC typically used to process the I and Q components in parallel signal paths.