Shared Victim Cache Lines in Multi-Core Processors
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Solution Overview
Problem
Microprocessor architectures face challenges in improving performance while reducing power consumption and cost, particularly in multiple core processors where cache memory integration leads to increased transistor usage and latency issues due to the need for separate caches for each core.
Innovation Solution
Implementing a processor architecture where victim lines from a full cache memory of one processor core can be stored in the cache memory of another processor core, reducing the need for higher-level caches and minimizing latency by allowing direct data transfer between cores, with logic to evaluate cache priority rules for efficient data management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate L1 and L2 caches are provided for each processor core, then each core can access cache memory independently, but the number of transistors increases and power consumption increases
Solution Approach 1:
The patent merges cache memory resources across multiple processor cores by allowing cores to share victim lines in each other's L1 caches. Instead of each core having dedicated separate caches, the system enables cooperative caching where cores can store evicted data in neighboring cores' cache memory, thereby reducing the total number of transistors required while maintaining cache access independence through the sharing mechanism.
2Reliability
If separate L1 and L2 caches are provided for each processor core, then cache access independence is maintained, but device complexity increases
Solution Approach 1:
The patent implements universality by enabling L1 cache memory to serve multiple functions: it acts as the primary cache for its associated core while also serving as a potential storage location for victim lines from other cores. This multi-functional approach reduces the need for separate dedicated caches for each core, thereby reducing device complexity while maintaining the ability for independent cache access through the shared victim line mechanism.
3Reliability
If victim lines are written back to system memory or higher-level cache, then cache coherence is maintained, but latency increases
Solution Approach 1:
The patent introduces an intermediary mechanism where neighboring processor cores act as intermediate storage for victim lines. Instead of immediately writing victim lines back to system memory or higher-level cache (which introduces latency), the system uses other cores' L1 cache memory as an intermediate destination. This intermediary approach maintains cache coherence while reducing latency by leveraging the fast inter-core communication path and available cache space in neighboring cores.
Data Source
AI summary
A processor includes multiple processor core units, each including a processor core and a cache memory. Victim lines evicted from a first processor core unit's cache may be stored in another processor core unit's cache, rather than written back to system memory. If the victim line is later requested by the first processor core unit, the victim line is retrieved from the other processor core unit's cache. The processor has low latency data transfers between processor core units. The processor transfers victim lines directly between processor core units' caches or utilizes a victim cache to temporarily store victim lines while searching for their destinations. The processor evaluates cache priority rules to determine whether victim lines are discarded, written back to system memory, or stored in other processor core units' caches. Cache priority rules can be based on cache coherency data, load balancing schemes, and architectural characteristics of the processor.