CMOS Integrated Circuit Deep Doping Well Noise Reduction
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Solution Overview
Problem
CMOS integrated circuits with separate circuit parts for digital and radio functions face challenges in reducing digital noise and leakage currents during sleep modes, where one part is turned off while the other remains voltage-supplied, due to electrical coupling of deep doping wells and limited substrate layout compatibility.
Innovation Solution
A continuous deep doping well extends across both circuit parts, with an electrically conducting path merging their power supplies and a switching unit that couples or isolates highly doped terminals to manage power states, allowing for reduced digital noise and efficient power management, including a voltage adaptation module for reduced power consumption in sleep mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If separate deep doping wells are provided for each circuit part to reduce digital noise, then digital noise reduction is improved, but circuit layout compatibility deteriorates due to limited separating distance
Solution Approach 1:
The patent merges the deep doping wells of the first and second circuit parts into a single common deep doping well. This allows both circuit parts to share the same noise-reduction structure, eliminating the need for separate wells and thereby resolving the layout compatibility issue while maintaining digital noise reduction effectiveness.
Solution Approach 2:
The common deep doping well serves multiple functions: it reduces digital noise for both circuit parts simultaneously and provides a shared structural foundation that accommodates the limited substrate layout. This multi-functional approach resolves the contradiction between noise reduction and layout compatibility.
2Loss of energy
If a switching unit is added to manage power states of separate circuit parts, then power consumption is reduced in sleep mode, but device complexity increases
Solution Approach 1:
The patent merges the power supply management of both circuit parts through a single switching unit that controls the common deep doping well. This unified approach reduces the number of switching units needed compared to managing separate wells independently, thereby reducing device complexity while still achieving power consumption reduction in sleep mode.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces digital noise and leakage currents, enabling one circuit part to be powered down while the other remains active, with compatible circuit layout and reduced power consumption, suitable for mobile communication devices.
Implementation Method 1
the provision of a deep doping well in a CMOS circuit with digital functions is efficient for reducing the noise which is generated by the operation of the digital circuit
Implementation Method 2
the leakage current in the periphery logic is suppressed during the sleep mode of the RAM circuit
Data Source
AI summary
An integrated circuit includes first and second circuit parts that may be arranged close to one another in a single semiconducting substrate. The circuit may use a deep doping well for reducing digital noise, and may implement a sleep mode for reducing power consumption. This circuit may have a random access memory, and may be a radio communication system-on-chip device. The integrated circuit may advantageously be used within a mobile communication apparatus.