Clock Generation Circuitry for Memory DVFS via Level Shifting
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Solution Overview
Problem
Existing memory devices face limitations in Dynamic Voltage Frequency Scaling (DVFS) due to constraints in voltage rail management, particularly with bitcell retention voltage and internal circuitry, which hampers overall power savings in integrated circuits.
Innovation Solution
The implementation of efficient clock generation circuitry that supports large range level shifting across multiple voltage domains, utilizing level shift circuitry and clock generator pulse circuitry with transistors to manage clock signals and chip enable signals across different voltage supplies, enabling dynamic voltage frequency scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If VDDPE is lowered to enable power savings, then power consumption is reduced, but voltage difference between VDDCE and VDDPE becomes small which limits overall power savings
Solution Approach 1:
The patent segments the clock generation function into two independent circuits: one receiving clock signals from VDDCE domain and another from VDDPE domain. This segmentation allows each circuit to operate independently at its respective voltage domain, enabling VDDPE to be lowered to 0.6V while VDDCE remains at 1.2V, thus achieving larger voltage difference and greater power savings.
Solution Approach 2:
The patent introduces level shift circuitry as an intermediary component that interfaces between the VDDCE domain and VDDPE domain. The level shift circuitry translates clock signals and control signals between different voltage domains, enabling the dual-rail architecture to function properly with large voltage difference between the two domains.
2Adaptability or versatility
If dual voltage rails are implemented to enable DVFS, then voltage flexibility is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal dual-rail clock generation architecture where separate clock generation circuits can serve multiple functions: generating clock signals for different voltage domains, supporting DVFS operations, and providing timing signals for memory operations. This multi-functionality reduces the need for additional dedicated circuits for each function.
Solution Approach 2:
The level shift circuitry serves as a universal intermediary that handles multiple signal types (clock signals, chip enable signals, timing signals) between voltage domains. This single intermediary component manages all cross-domain communications, simplifying the overall system architecture compared to having separate translation circuits for each signal type.
3Reliability
If VDDCE is held at higher voltages for bitcell retention, then retention reliability is improved, but overall power savings are limited
Solution Approach 1:
The patent segments the memory system into two independent voltage domains: VDDCE for bitcell core circuitry and VDDPE for periphery circuitry. This segmentation allows VDDCE to be maintained at higher voltage (1.2V) for reliable bitcell retention while VDDPE can be lowered (0.6V) for power savings in peripheral operations, achieving both retention reliability and power efficiency.
Solution Approach 2:
The patent applies different voltage levels to different parts of the memory system based on their specific requirements: higher voltage (VDDCE) is applied to the bitcell core where retention reliability is critical, while lower voltage (VDDPE) is applied to peripheral circuitry where power consumption is the primary concern. This local quality approach optimizes both reliability and power efficiency.
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit having level shift circuitry that receives a clock signal in a first voltage domain from a first voltage supply and provides a level shifted clock signal in a second voltage domain based on a second voltage supply that is different than the first voltage supply. The integrated circuit may include clock generator pulse circuitry that receives the clock signal in the first voltage domain from the first voltage supply and receives the level shifted clock signal in the second voltage domain from the level shift circuitry.