Multi-Phase Clock Generation with Coarse-Fine Delay Loops
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Solution Overview
Problem
Existing clock generation circuits in semiconductor devices require high power consumption to maintain accurate phase and minimize phase skew among output clock signals, which contradicts the trend towards low power consumption.
Innovation Solution
A clock generation circuit comprising a delay loop circuit with a coarse delay circuit, a fine delay circuit, a replica, a phase detector, and a delay control circuit, which generates multiple output clock signals by mixing phases and adjusting delays based on phase detection signals, allowing for power-efficient operation by selectively activating high and low power consumption delay loop circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-performance clock generation circuit (phase-locked loop or delay-locked loop) is used to generate multi-phase clock signals with constant phase difference, then the phase accuracy and phase skew are improved, but the power consumption increases
Solution Approach 1:
The delay-locked loop is divided into two independent sub-loops: a coarse delay loop for initial phase alignment and a fine delay loop for precise phase adjustment. Each sub-loop operates with different power consumption levels, allowing the system to achieve accurate phase synchronization while reducing overall power consumption compared to a single high-performance loop.
Solution Approach 2:
The system dynamically switches between coarse and fine delay adjustments based on locking status. During acquisition, the coarse loop is active for rapid phase alignment; during tracking, the fine loop takes over for precise maintenance. This dynamic operation allows the circuit to consume less power while maintaining phase accuracy throughout different operational phases.
2Stability of the object's composition
If a high-performance clock generation circuit is used to minimize phase skew among output clock signals, then the synchronization quality is improved, but the power consumption increases
Solution Approach 1:
The clock generation system is segmented into multiple delay loop circuits, each responsible for generating specific phase relationships. The coarse delay loop handles bulk phase alignment while the fine delay loop refines the synchronization. This segmentation allows each sub-circuit to operate at lower power while collectively achieving the synchronization quality of a single high-performance loop.
Solution Approach 2:
Instead of using one loop to perform all delay adjustments, the system uses two loops where each performs only part of the work. The coarse loop handles the majority of phase correction (excessive action for initial alignment), while the fine loop handles minor adjustments. This partial division of labor reduces the burden on each individual loop, lowering overall power consumption while maintaining synchronization quality.
Data Source
AI summary
A delay circuit including a first output clock generation circuit and a second output clock generation circuit. The first output clock generation circuit generates a first output clock signal by mixing phases of a first clock signal and a second clock signal based on an (n+1)-th generated delay control signal. The second output clock generation circuit generates a second output clock signal by mixing the phases of the first and second clock signals based on both an n-th generated delay control signal and the (n+1)-th generated delay control signal.