Clock Generation Circuit Partial Enable Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in controlling processing performance and power consumption, as they can only be adjusted in fixed ratios (1/N) of clock frequency, which limits flexibility and efficiency, especially in small portable devices where power management is critical.
Innovation Solution
A semiconductor device with a clock generation circuit that allows partial or complete prohibition of a source clock signal, enabling the generation of clock signals with frequencies other than 1/N, thereby allowing for flexible control of throughput and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock frequency is divided by 1/N to reduce power consumption, then power consumption decreases, but processing performance can only be adjusted in fixed ratios (1, 1/2, 1/4, etc.)
Solution Approach 1:
The clock signal is segmented into multiple individual clock pulses within one cycle of the reference clock signal. By selectively enabling or disabling specific clock pulses using clock enable signals, the patent achieves fine-grained control over the number of active clock cycles, allowing processing performance and power consumption to be adjusted in arbitrary ratios rather than fixed 1/N divisions.
Solution Approach 2:
Instead of completely enabling or disabling the clock signal in fixed divisions, the patent applies partial action by selectively enabling only certain clock pulses within a reference clock cycle. This allows the system to operate at any desired performance level between 0% and 100% of the reference clock frequency, providing continuous rather than discrete control options.
2Use of energy by moving object
If clock frequency is reduced to control power consumption, then power consumption decreases, but system complexity increases due to clock switching operations
Solution Approach 1:
The patent combines multiple clock enable signals corresponding to different clock pulses into a single control mechanism. By using logic circuits to combine these enable signals, the system achieves fine-grained clock control without requiring separate complex switching operations for each individual clock pulse, thereby reducing overall system complexity while maintaining flexible power management.
3Ease of manufacture
If fixed 1/N clock division is used, then power consumption control is simplified, but processing performance cannot be optimized for specific application requirements
Solution Approach 1:
The patent implements dynamic clock control where the number of enabled clock pulses can be adjusted in real-time based on application requirements. Unlike fixed 1/N division, this dynamic approach allows the system to adaptively optimize processing performance for different workloads while maintaining simplified power management through programmable control registers that define which clock pulses should be enabled.
Data Source
AI summary
It is to provide a technique capable of controlling the throughput and the power consumption of a semiconductor device at a desired ratio. A semiconductor device includes a clock generation circuit that generates a clock signal and a data processing unit that receives the clock signal. The clock generation circuit includes an oscillator that generates a source clock signal, an output circuit that outputs a clock signal with the source clock signal enabled, and a control circuit having a setting circuit in which the data processing unit sets the ratio of the enable. The semiconductor device can change the frequency of the clock signal by partially permitting or prohibiting the source clock signal in time.