Clock Generator Phase Adjustment for High-Speed JESD Clocks
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Solution Overview
Problem
Conventional JESD204B/C systems require all clocks in a clock domain to be stopped and restarted for dynamic phase adjustment of one device clock, leading to reduced system performance and efficiency.
Innovation Solution
A clock generator circuit with an integer divider, digital delay stage, and analog delay stage, along with math engine circuitry, allows for dynamic phase adjustment of device clocks or system reference signals without affecting other clocks in the domain, enabling fine fractional resolution and minimal timing glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional phase adjustment methods are used in JESD204B/C systems, then phase offset can be applied to device clocks, but all other clocks in the clock domain must be stopped and restarted, reducing system performance and efficiency
Solution Approach 1:
The clock domain is segmented into independent clock generators, each capable of autonomous phase adjustment. The system divides the monolithic clock control into separate controllable units (first clock generator, second clock generator, etc.), allowing one generator to adjust phase without affecting others. This segmentation enables localized phase correction while maintaining continuous operation of other clocks in the domain.
Solution Approach 2:
The patent implements dynamic phase adjustment capability where clock generators can modify their output phase in real-time without system shutdown. The system transitions from static phase configuration to dynamic adjustment, allowing phase offsets to be applied on-the-fly during operation, thereby maintaining productivity while achieving precise phase control.
2Measurement precision
If phase adjustment is applied to a system reference clock, then the reference phase can be corrected, but all system reference modules throughout the clock domain must be shut down and resynchronized
Solution Approach 1:
The system separates reference clock generation from device clock generation, with each clock generator having its own independent reference clock input. This allows individual reference clock modules to adjust their phase without requiring system-wide shutdown, as other reference modules continue operating independently.
Solution Approach 2:
Each clock generator is equipped with local phase adjustment capability through fractional dividers and delay elements, enabling localized phase correction without propagating disruption throughout the entire system. The quality adjustment is applied locally at each generator rather than requiring centralized control that would halt all modules.
3Speed
If high speed clock distribution is implemented, then data communication rates can be increased, but constraints on clock parameters such as noise, jitter, and duty cycle stability become more stringent
Solution Approach 1:
The system employs fractional dividers that can dynamically change division ratios with fine resolution (e.g., 1/64 or 1/128 steps), allowing precise control of output clock frequency and phase. This parameter adjustment capability enables the system to optimize clock characteristics for high-speed operation while maintaining stability through controlled, incremental changes rather than abrupt adjustments.
Solution Approach 2:
The patent implements phase-locked loop (PLL) mechanisms that provide feedback control for clock generation. The PLL continuously monitors and adjusts the output clock phase and frequency to match the reference clock, thereby maintaining duty cycle stability and reducing jitter even at high operating speeds where these parameters are critical.
Data Source
AI summary
A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value. The clock generator circuit may be implemented in a clock domain of a system along with one or more other clock generator circuits that each generate an output clock based on a reference clock generated by a reference clock source, such as a phase-locked loop.