Clock-Guided Logic Precharge for Lower Path Switching Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for optimizing signal path delays in integrated circuits, such as output prediction logic (OPL), face challenges including complex clock signal generation, significant clocking overhead, and sensitivity to process variations and noise, which hinder their adoption due to the need for precise delay locked loops and elaborate clock networks.
Innovation Solution
The implementation of Clock Guided Logic (CGL) in integrated circuits, where every Nth logic element is either an evaluate-high (EVH) or evaluate-low (EVL) element, alternated between EVH and EVL types, reduces switching delays by precharging outputs and optimizing clock signal generation, allowing for simpler clock path design and reduced noise sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If output prediction logic (OPL) is used to reduce switching delays, then path switching delay is reduced, but clock signal generation complexity increases
Solution Approach 1:
The patent segments the logic path into groups of N logic elements, inserting a clocked logic element at every Nth position. This segmentation allows selective precharging of specific nodes without requiring complex clocking of every logic element, thereby reducing switching delay in critical paths while keeping clock generation manageable.
Solution Approach 2:
The patent applies preliminary action by precharging the output of logic elements at every Nth position using clocked logic elements (EVH/EVL types) before the actual data signal arrives. This precharging prepares the circuit state in advance, reducing the switching delay when data transitions occur, while the periodic nature of precharging every Nth element keeps the clocking overhead acceptable.
2Loss of time
If output prediction logic (OPL) is used to reduce switching delays, then path switching delay is reduced, but clocking overhead increases
Solution Approach 1:
Instead of applying dynamic logic precharging to every logic element (excessive action), the patent applies it selectively to every Nth logic element (partial action). This partial application is sufficient to reduce switching delays in critical paths while significantly reducing the clocking overhead and energy consumption compared to full-path dynamic logic.
Solution Approach 2:
The patent changes the parameter of clocking frequency by using a lower frequency clock signal for the clocked logic elements compared to what would be required if every logic element were clocked. The clock period is set to T/2 where T is the evaluation period, allowing the same switching delay reduction effect with reduced clocking overhead.
3Loss of time
If output prediction logic (OPL) is used to reduce switching delays, then path switching delay is reduced, but sensitivity to process variations and noise increases
Solution Approach 1:
The patent introduces stable logic elements (non-clocked logic elements) as intermediaries between the clocked logic elements. These intermediary stable logic elements filter out noise and glitches that might be generated by the clocked elements, while still allowing the precharging effect to reduce switching delays. This intermediary structure improves reliability by isolating the sensitive clocked elements from the rest of the circuit.
4Loss of time
If every Nth logic element is made clocked to reduce switching delays, then path switching delay is reduced, but device complexity increases
Solution Approach 1:
The patent designs the clocked logic elements (EVH and EVL types) to be universal building blocks that can be inserted at any Nth position in a logic path regardless of the specific logic function. These multi-functional elements can serve as precharge elements, buffer elements, or logic elements depending on the circuit configuration, reducing the need for specialized circuit designs for each position and thereby managing overall device complexity.
Data Source
AI summary
Methods and apparatuses for optimizing switching delay in integrated circuits are described. Combinational logic gates are modified with precharge circuitry and instantiated in order to reduce switching transitions of circuit elements in a signal path.