Heterogeneous Clock IC Calibration for Low-Power Frequency Accuracy
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Solution Overview
Problem
Existing clock integrated circuits face challenges in generating accurate clock signals while minimizing the number of crystal oscillators, which are large and consume high power, and require a more integrated and power-efficient solution.
Innovation Solution
A clock integrated circuit that includes a crystal oscillator for high-frequency signals and an RC oscillator with a frequency divider and calibration circuit for low-frequency signals, allowing for frequency adjustment based on temperature and operation mode to generate accurate clock signals with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a crystal oscillator is used to generate clock signals, then the clock signal characteristics against noise are improved, but the design area and power consumption increase
Solution Approach 1:
The patent divides the clock signal generation into two segments: a crystal oscillator for generating a first clock signal (main clock) and an RC oscillator for generating a second clock signal (sub clock). This segmentation allows each oscillator to be optimized for its specific function, reducing the overall power consumption while maintaining signal quality where needed.
Solution Approach 2:
The patent makes the crystal oscillator serve multiple functions by using it to generate both the first clock signal for IP processing and the second clock signal for time measurement and system control. This multi-functionality eliminates the need for a separate crystal oscillator for low-frequency signals, reducing design area and power consumption.
2Reliability
If a crystal oscillator is used to generate clock signals, then the clock signal characteristics against noise are improved, but the design area increases
Solution Approach 1:
The patent segments the clock generation responsibilities by using an RC oscillator for the second clock signal (low-frequency sub clock) instead of requiring a second crystal oscillator. This segmentation significantly reduces the design area while maintaining the high-quality crystal oscillator only where needed for main processing.
Solution Approach 2:
The crystal oscillator is designed to serve dual purposes: generating the first clock signal for IP operations and providing the second clock signal for timekeeping and system control. This universality eliminates redundant hardware, reducing the overall design area of the integrated circuit.
3Use of energy by moving object
If an RC oscillator is used to generate low-frequency clock signals, then the power consumption and design area are reduced, but the frequency accuracy decreases
Solution Approach 1:
The patent implements a feedback mechanism where the first clock signal from the crystal oscillator is used to calibrate the second clock signal from the RC oscillator. The calibration circuit adjusts the RC oscillator's output based on the accurate crystal reference, ensuring frequency accuracy is maintained despite using the lower-power RC oscillator.
Solution Approach 2:
The patent changes the operational parameters of the RC oscillator through calibration based on the crystal oscillator's accurate frequency reference. By adjusting the RC oscillator's frequency parameters using feedback from the crystal oscillator, the system achieves both low power consumption and high frequency accuracy.
Data Source
AI summary
A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.