Multi-Phase Clock Interpolation for Low-Error Memory Timing
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Solution Overview
Problem
High-speed semiconductor memory devices face challenges in generating multi-phase clock signals with reduced current consumption and minimal phase errors, especially as clock signal frequencies increase, leading to phase offsets and reduced valid data transmission windows.
Innovation Solution
A multi-phase clock generating circuit with a phase correction block and clock control block that produce interpolated phase clock signal groups using digital control signals and enable signals to correct phase errors, allowing selective output of optimized multi-clock signals, reducing current consumption and phase errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If phase interpolators are used to generate multi-phase clock signals, then current consumption is reduced compared to feedback loop circuits, but phase errors increase as clock frequency increases
Solution Approach 1:
The phase correction block divides the correction of phase errors into multiple stages, with each phase interpolation unit handling a portion of the correction process. This segmented approach allows for more precise phase adjustment at high frequencies while maintaining low current consumption by only activating necessary correction stages.
Solution Approach 2:
The circuit dynamically adjusts the number of active phase interpolation units based on the detected phase error magnitude. When phase errors are large, more units are activated; when errors are small, fewer units are needed. This dynamic adaptation optimizes both phase accuracy and current consumption across different operating conditions.
2Measurement precision
If the number of phase interpolation units is increased to reduce phase errors, then phase accuracy improves, but current consumption and circuit complexity increase
Solution Approach 1:
The control unit dynamically determines the number of active phase interpolation units based on the phase error detected by the phase detector. This dynamic configuration allows the circuit to use more units when high precision is needed and fewer units when lower precision suffices, optimizing the trade-off between phase accuracy and current consumption.
Solution Approach 2:
The circuit changes the operational parameter of the phase interpolation block by adjusting the number of active units based on phase error magnitude. This parameter change allows the same hardware structure to operate at different precision levels, reducing current consumption when full precision is not required.
3Measurement precision
If feedback loop circuits (PLL or DLL) are used to generate multi-phase clock signals, then phase accuracy is maintained, but current consumption and circuit area increase significantly
Solution Approach 1:
The invention extracts only the essential phase correction function from the complex feedback loop circuits (PLL/DLL), implementing a simplified open-loop phase interpolation system with selective correction units. This extraction maintains sufficient phase accuracy for the application while eliminating the excessive current consumption and area requirements of full feedback loops.
Solution Approach 2:
The phase interpolation units are designed as simpler, lower-cost components compared to feedback loop circuits. Multiple such units can be activated when needed for high accuracy, but the system can also operate with fewer or no correction units when lower accuracy suffices, providing a cost-effective alternative to always-using complex feedback loops.
Data Source
AI summary
A multi-phase clock signal generating circuit includes a phase correction block configured to receive multi-phase clock signals and produce a plurality of interpolated phase clock signal groups in which the phases of the multi-phase clock signals are differently controlled. The multi-phase clock signals are out of phase with each other. A clock control block is configured to produce output multi-clock signals by selectively outputting one among the interpolated phase clock signal groups using a digital control signal having a plurality of bits which are produced based on phase differences of the multi-phase clock signals.