Clock Path Jitter Compensation Using Bias-Controlled Delay Elements
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Solution Overview
Problem
Memory devices experience clock jitter due to variations in power supply voltage and current, which affect the synchronization of operations and can lead to time variations in clock signals and outputs, despite operating within specified parameters.
Innovation Solution
Incorporating jitter compensation circuits within the clock path that adjust delay based on bias currents or voltages to mitigate power supply-induced sensitivity, using bias-controlled delay elements and phase mixing of clock paths to maintain synchronization and reduce phase jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory devices operate within specified power supply parameters, then proper operation is maintained, but clock jitter still occurs due to sensitivity variations in clock path components
Solution Approach 1:
The patent changes the delay parameter of clock path constituents dynamically in response to detected jitter. The delay adjustment mechanism modifies the timing characteristics of clock signals to compensate for power supply-induced variations, thereby maintaining precise clock timing despite operating within standard power parameters.
Solution Approach 2:
The patent implements a feedback mechanism that detects clock jitter and uses this information to adjust delay settings in clock path constituents. The detection circuit monitors timing variations and feeds this information back to the delay adjustment mechanism, creating a closed-loop system that continuously compensates for jitter.
2Measurement precision
If delay adjustment is applied to compensate for power supply variations, then clock jitter is reduced, but device complexity increases
Solution Approach 1:
The patent introduces dynamic adjustment capability to clock path constituents, allowing delay parameters to be modified in response to detected jitter. This dynamic behavior enables the system to adapt to varying power supply conditions without requiring a completely redesigned clock distribution architecture.
Solution Approach 2:
The patent segments the clock path into adjustable delay elements that can be independently controlled. By dividing the clock distribution network into controllable segments, the system can apply targeted delay adjustments to specific constituents without affecting the entire clock tree, thereby managing complexity more effectively.
Data Source
AI summary
Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response.